System Management Microcontroller

5

ELECTRICAL CHARACTERISTICS: JTAG INTERFACE

negative.

Note 2: This value does not include current in SDA, SCL, and P6.0–P6.4.

Note 3: Guaranteed by design.

Note 4: ADCCLK = SYSCLK/16. This is following an initial startup time of approximately 80µs.

Note 5: Base line accuracy of reference source + 0.25% introduced by the MAX31782.

Note 6: The voltage applied to the pins must not exceed their corresponding absolute maximum voltages.

Note 7: ADC has no missing codes.

Note 9: After this period, the first clock pulse can be generated.

to bridge the undefined region of the falling edge of SCL.

Note 12: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.

SCL

SDA

STOP

START

REPEATED

START

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

JTAG Logic Reference

V

TCK High Time

1

F

s

TCK Low Time

1

F

s

TCK Low to TDO Output

0.125

F

s

TMS, TDI Input Setup to TCK

High

0.30

F

s

TMS, TDI Input Hold after TCK

High

0.25

F

s