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LP5907UVE-4.5-NOPB Datasheet(PDF) 2 Page - Texas Instruments |
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LP5907UVE-4.5-NOPB Datasheet(HTML) 2 Page - Texas Instruments |
2 / 21 page N/C 1 2 3 5 4 EN GND VIN VOUT SVA-30180519 W B2 B1 A2 A1 VOUT GND VIN VEN B2 B1 A2 A1 VOUT GND VIN VEN TOP VIEW BOTTOM VIEW TOP MARKING SVA-30180502 LP5907 SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAMS 4-Bump Ultra-Thin micro SMD Package Note: The actual physical placement of the package marking will vary from part to part. 5-Pin SOT23 Package (Top View) PIN DESCRIPTIONS MICRO SOT23 NAME SMD DESCRIPTION PIN NO. PIN NO. VIN A1 1 Input voltage supply. A 1-µF capacitor should be connected at this input. Output voltage. A 1-µF Low ESR capacitor should be connected to this pin. Connect this output to VOUT A2 5 the load circuit. An internal 280- Ω discharge resistor prevents a charge remaining on VOUT when VEN is low. VEN B1 N/A Enable input; disables the regulator when ≤0.4 V. Enables the regulator when ≥1.2 V. An internal 1-M Ω pulldown resistor connects this input to ground. EN N/A 3 GND B2 2 Common ground N/C N/A 4 No connect pin 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 |
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