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W89C926 Datasheet(PDF) 4 Page - Winbond |
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W89C926 Datasheet(HTML) 4 Page - Winbond |
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4 / 48 page  W89C926 PENTIC+ - 4 - Pin Description, continued NAME NUMBER TYPE DESCRIPTION OE 35 I/TTL Output Enable: The OE line is asserted by the system to obtain memory read data from the card memory. It has an internal 100K ohm pull-high resistor. CE1,2 39, 36 I/TTL Card Enable: CE1,2 are asserted by the system for data bus width control as shown below. These pins have an internal 100K ohm pull-high resistor. CE2 CE HD15-HD8 HD7-HD0 0 0 1 1 0 1 0 1 Valid Valid High-Z High-Z Valid High-Z Valid High-Z REG 11 I/TTL Register & I/O selection: REG is asserted by the system to access attribute memory or I/O space. It remains high inactive for common memory accesses. It has an internal 100K ohm pull-high resistor. IOIS16 100 O/TTL 16-bit I/O access: Asserted by the PENTIC+ to inform the system that current operation is a 16-bit I/O access. INPACK 13 O/TTL Input Acknowledge: Asserted by the PENTIC+ when it has been selected and can respond to an I/O read cycle. WAIT 17 O/TTL Wait State: Asserted by the PENTIC+ to insert wait states into current memory or I/O access cycles. RESET 19 I/TTL Card Reset: A RESET pulse will initiate the PENTIC+'s initialization procedure, including auto-ID/configuration loading, register initialization, and state machine initialization. The pulse width should be at least 500 nS to be recognized as a valid reset. This pin has an internal 100K ohm pull-up resistor. |
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Similar Description - W89C926 |
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