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W83628F Datasheet(PDF) 11 Page - Winbond |
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W83628F Datasheet(HTML) 11 Page - Winbond |
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11 / 25 page  W83628F & W83629D Publication Release Date: May 18, 2005 - 11 - Revision A1 4.1.3 ISA Interface Signals, contiuned SYMBOL PIN I/O FUNCTION MEMR# 6 I/O24t Memory Read. MEMR# asserted indicates the current ISA bus cycle is a memory read. MEMW# 7 I/O24t Memory Write. MEMW# asserted indicates the current ISA bus cycle is a memory write. MASTER# 17 INt MASTER#. This signal is used with a DREQ line by an ISA master to gain control of the ISA Bus. LA[23:17] 5-2 127- 125 I/O24t Unlatched Address. The LA[23:17] address lines are bi- directional. These address lines allow accesses to physical memory on the ISA Bus up to 16 Mbytes. LA[23:17] are outputs when the W83628F owns the ISA Bus. ROMCS# 73 I/O12 ROMCS# ,this pin weak pulled-down during PCIRST is asserted, and apply a pull-up resistor (4.7 Kohm) to this pin enable positive decoder of BIOS address range (depend on Configure register 70 , bit 3,2). When BIOS assress range is enabled , the PIN is BIOS ROM CS# output. REFRESH# 75 I/O24t Refresh. REFRESH# asserted indicates that a refresh cycle is in progress, or that an ISA master is requesting W83628F to generate a refresh cycle. Upon PCIRST#, this signal is tri-stated. ZEROWS# 106 INt Zero Wait States. An ISA slave asserts ZEROWS# after its address and command signals have been decoded to indicate that the current cycle can be executed as an ISA zero wait state cycle. ZEROWS# has no effect during 16-bit I/O cycles. SMEMR# 117 OUT24t Standard Memory Read. SMEMR# asserted indicates the current ISA bus cycle is a memory read cycle to an address below 1 Mbyte. SMEMW# 119 OUT24t Standard Memory Write. SMEMW# asserted indicates the current ISA bus cycle is a memory write cycle to an address below 1 Mbyte. BALE 122 OUT24t Bus Address Latch Enable. BALE is an active high signal asserted by the W83628F to indicate that the address (SA[19:0], LA[23:17]) and SBHE# signal lines are valid. The LA[23:17] address lines are latched on the trailing edge of BALE. BALE remains asserted throughout DMA and ISA master cycles. BALE is driven low upon PCIRST#. MEMCS16# 123 OD24 Memory Chip Select 16. MEMCS16# asserted indicates that the memory slave supports 16-bit accesses. 7.1.4 Power Signals SYMBOL PIN I/O FUNCTION VCC 1, 82, 102, 115 PWR 5V Supply. 3VCC 27, 46, 64 PWR 3.3V Supply. GND 16, 38, 50, 65, 95, 111, 128 PWR Ground. |
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