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W83628F Datasheet(PDF) 9 Page - Winbond |
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W83628F Datasheet(HTML) 9 Page - Winbond |
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9 / 25 page  W83628F & W83629D Publication Release Date: May 18, 2005 - 9 - Revision A1 4.1.1 PCI Interface, contiuned SYMBOL PIN I/O FUNCTION FRAME# 40 I/O24tp3 Frame Signal. FRAME# is driven by the current PCI bus master to indicate the beginning and duration of an access. IDSEL 29 INt Initialization Device Select. IDSEL is used as a chip select during configuration read and write transactions. This signal should be externally tied to one of the upper 21 address signals. STOP# 39 I/O12tp3 Bus Stop#. STOP# indicates the current target is requesting the master to stop the current PCI bus transaction. IRDY# 41 I/O12tp3 Initiator Ready. IRDY# indicates the initiating agent ability to complete the current data phase of the PCI bus transaction. TRDY# 42 I/O12tp3 Target Ready. TRDY# indicates the target agent’s ability to complete the current data phase of the PCI bus transaction. DEVSEL# 43 I/O12tp3 Device Select. W83628F drives DEVSEL# to indicate that it is the target of the current PCI bus transaction. W83628F uses subtractive decoding and the NOGO protocol to claim PCI transactions. SERR# 45 OD12 System Error. SERR# can be pulsed active by any PCI agent that detects a system error condition. PAR 49 I/O12tp3 Parity Signal. W83628F generates even parity across AD[31:0] and C/BE[3:0]#. PCIRST# 71 INt PCI Reset. W83628F receives PCIRST# as a reset from the PCI Bus. 7.1.2 Control Logic and Handshaking Signals SYMBOL PIN I/O FUNCTION HS[2:0] 112- 114 I/O12 Handshaking Signals. HS[2:0] connected to W83629D for PCI to ISA SET handshaking signals. HS1 is handshaking Signal 1, this pin weak pulled-down during PCIRST# is asserted, and apply a pull-up resistor(4.7Kohm) to this pin disables ISA bridge subtraction decoder. ISOLATE# 72 INt Isolation Control Input. Isolate# is an active low signal by user programming to control the W83628F all output signals to Isolation and Tri-state. NOGO 76 INt NOGO, This signal indicates which master initiated the current transaction and also indicates whether or not the current bus cycle is targeted for the ISA bus. This signal is a point-to-point connection between PCI HOST Bridge and W83628F. |
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