W83194BR-KT

PRELIMINARY

Publication Release Date: June 2000

- 9 -

Revision 0.43

7.2.2 Register 1 : CPU Clock Register (1 = enable, 0 = Stopped)

Bit

@PowerUp

Pin

Description

7

1

-

Reserved

6

1

-

1=center type S.S.T.

0= 0-0.5% down type S.S.T.

5

0

-

0 = Normal

1 = Spread Spectrum enabled

4

0

-

0 = ±0.25% Spread Spectrum Modulation

1 = ±0.5% Spread Spectrum Modulation

3

1

-

Reserved

2

1

40

SDRAM12 (Active / Inactive)

1

1

43

44

CPUT0

CPUC0 (Active / Inactive)

0

1

46

CPUT_CS (Active / Inactive)

7.2.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped)

Bit

@PowerUp

Pin

Description

7

1

-

Reserved

6

1

7

PCICLK_F (Active / Inactive)

5

1

-

Reserved

4

1

13

PCICLK5 (Active / Inactive)

3

1

12

PCICLK4 (Active / Inactive)

2

1

11

PCICLK3 (Active / Inactive)

1

1

10

PCICLK2 (Active / Inactive)

0

1

8

PCICLK1 (Active / Inactive)

7.2.4 Register 3: SDRAM, 24MHz, 48MHz Clock Register ( 1 = enable, 0 = Stopped )

Bit

@PowerUp

Pin

Description

7

1

48

REF1 (Active / Inactive)

6

1

2

REF0 (Active / Inactive)

5

1

26

48MHz (Active / Inactive)

4

1

25

24_48MHz (Active / Inactive)

3

1

17

SDRAM11 (Active / Inactive)

2

1

18

SDRAM10 (Active / Inactive)

1

1

20

SDRAM 9 (Active / Inactive)

0

1

21

SDRAM 8 (Active / Inactive)