W83194AR-73

PRELIMINARY

Publication Release Date: May 1999

- 5 -

Revision 0.30

5.4 Register 3: PCI Clock Register (1 = Active, 0 = Inactive)

Bit

@PowerUp

Pin

Description

7

1

20

PCICLK7 (Active / Inactive)

6

1

19

PCICLK6 (Active / Inactive)

5

1

17

PCICLK5 (Active / Inactive)

4

1

16

PCICLK4 (Active / Inactive)

3

1

15

PCICLK3 (Active / Inactive)

2

1

13

PCICLK2 (Active / Inactive)

1

1

12

PCICLK1 (Active / Inactive)

0

1

11

PCICLK0 (Active / Inactive)

5.5 Register 4: Additional Register (1 = Active, 0 = Inactive)

Bit

@PowerUp

Pin

Description

7

X

-

SEL_3V66#

6

1

8

3V66_1(Active / Inactive)

5

1

7

3V66_0(Active / Inactive)

4

0

-

Reserve

3

1

47

IOAPIC (Active / Inactive)

2

X

-

FS1#

1

1

44

CPUCLK1(Active / Inactive)

0

1

45

CPUCLK0(Active / Inactive)

5.6 Register 5: Reserve Register

Bit

@PowerUp

Pin

Description

7

0

-

Reserve

6

0

-

Reserve

5

0

-

Reserve

4

0

-

Reserve

3

0

-

Reserve

2

0

-

Reserve

1

0

-

Reserve

0

0

-

Reserve