Preliminary W83193R-02/-04/-04A

Publication Release Date: April 1999

- 5 -

Revision A1

6.0 FREQUENCY SELECTION

W83193R-02/-04 Frequency Table

FS2

FS1

FS0

CPU, SDRAM (MHz)

PCI (MHz)

REF, IOAPIC (MHz)

0

0

0

50

25

14.318

0

0

1

75

32

14.318

0

1

0

83.3

41.65

14.318

0

1

1

68.5

34.25

14.318

1

0

0

83.3

33.3

14.318

1

0

1

75

37.5

14.318

1

1

0

60

30

14.318

1

1

1

66.8

33.4

14.318

W83193R-04A Frequency Table

FS2

FS1

FS0

CPU, SDRAM (MHz)

PCI (MHz)

REF, IOAPIC (MHz)

0

0

0

50

25

14.318

0

0

1

100

50

14.318

0

1

0

83.3

41.65

14.318

0

1

1

68.5

34.25

14.318

1

0

0

90

45

14.318

1

0

1

75

37.5

14.318

1

1

0

112

56

14.318

1

1

1

66.8

33.4

14.318

7.0 CPU 3.3#_2.5 BUFFER SELECTION

CPU 3.3#_2.5 (PIN 2) INPUT LEVEL

CPU & IOAPIC OPERATE AT

1

0

8.0 FUNCTIONAL DESCRIPTION

8.1 Power Management Functions

All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,

external circuitry should allow 3 ms for the VCO to stabilize prior to enabling clock outputs to assure

correct pulse widths. When MODE = 0, pins 15 and 46 are inputs (PCI_STOP#), (CPU_STOP#),

when MODE = 1, these functions are not available. A particular clock could be enabled as both the 2-

wire serial control interface and one of these pins indicate that it should be enable.