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UCC27512 Datasheet(PDF) 5 Page - Texas Instruments |
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UCC27512 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 32 page UCC27511 UCC27512 www.ti.com SLUSAW9C – FEBRUARY 2012 – REVISED JUNE 2012 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT Supply voltage range, VDD 4.5 12 18 V Operating junction temperature range -40 140 °C Input voltage, IN+ and IN- 0 18 V THERMAL INFORMATION UCC27511 UCC27512 THERMAL METRIC SOT-23 (DBV) (1)WSON UNITS 6 PINS 6 PINS θJA Junction-to-ambient thermal resistance(2) 217.8 85.6 θJCtop Junction-to-case (top) thermal resistance(3) 97.6 100.1 θJB Junction-to-board thermal resistance(4) 72.2 58.6 °C/W ψJT Junction-to-top characterization parameter(5) 8.6 7.5 ψJB Junction-to-board characterization parameter(6) 71.6 58.7 θJCbot Junction-to-case (bottom) thermal resistance(7) n/a 23.7 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. NOTE Under identical power dissipation conditions, the DRS package will allow to maintain a lower die temperature than the DBV. θJA metric should be used for comparison of power dissipation capability between different packages (Refer to the APPLICATION INFORMATION Section). Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): UCC27511 UCC27512 |
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