Preliminary W78LE51

- 8 -

Continued

PS2 PS1 PS0

WATCHDOG TIME-OUT PERIOD

1

0

0

314.57mS

1

0

1

629.14 mS

1

1

0

1.25 S

1

1

1

2.50 S

Clock

The W78LE51 is designed to be used with either a crystal oscillator or an external clock. Internally,

the clock is divided by two before it is used. This makes the W78LE51 relatively insensitive to duty

cycle variations in the clock. The W78LE51 incorporates a built-in crystal oscillator. To make the

oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load

capacitor must be connected from each pin to ground. An external clock source should be connected

to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as

required by the crystal oscillator.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal

clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The

processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this

mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is

by a reset.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two

machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to

deglitch the reset line when the W78LE51 is used with an external RC network. The reset logic also

has a special glitch removal circuit that ignores glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of

bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

ON-CHIP MTP ROM CHARACTERISTICS

The W78LE51 has several modes to program the on-chip MTP-ROM. All these operations are

−A0(P2.7−P2.0,

P1.7

−P1.0) and the D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these

operations.

Read Operation

This operation is supported for customer to read their code and the Security bits. The data will not be

valid if the Lock bit is programmed to low.