W78C58

Publication Release Date: December 1997

- 9 -

Revision A5

* Interrupts

***IE - Interrupt Enable (A8H)

EA

-

ET2

ES

ET1

EX1

ET0

EX0

EA: lobal interrupt enable flag

ET2: Timer 2 overflow interrupt enable

ES:

Serial port interrupt enable

EX1: External interrupt 1 enable

ET1: Timer 1 overflow interrupt enable

EX0: External interrupt 0 enable

***IP - Interrupt Priority (B8H)

-

-

PT2

PS

PT1

PX1

PT0

PX0

PT2: Timer 2 interrupt priority high if set

PS:

Serial port priority high if set

PT1: Timer 1 interrupt priority high if set

PX1: External interrupt 1 priority high if set

PT0: Timer 0 interrupt priority high if set

PX0: External interrupt 0 priority high if set

***XICON - External Interrupt Control (C0H)

PX3

EX3

IE3

IT3

PX2

EX2

IE2

IT2

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

The W78C58 supports an eight-source and a four-priority-level interrupt architectures. Besides the

SFRs of IP and IE to control the six-source of the standard 8052 interrupt functions. There is an

another SFR (XICON) to control the extra two-source of the external interrrupt (INT2 and INT3). This

priority scheme is formed by combining IPH with IP to determine the priority of each interrupt. Except

the INT2 and INT3, they are not defined in IP