W49V002FA

Publication Release Date: February 19, 2002

- 3 -

Revision A2

FUNCTIONAL DESCRIPTION

Interface Mode Selection And Description

This device can be operated in two interface modes, one is Programmer interface mode, the other is

FWH interface mode. The IC pin of the device provides the control between these two interface

IC pin is set to high state, the device will be in the Programmer mode; while the IC pin is set to low

state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just

behaves like traditional flash parts with 8 data lines. But the row and column address inputs are

multiplexed, which go through address inputs A[10:0]. For FWH mode, It complies with the FWH

Interface Specification. Through the FWH[3:0] to communicate with the system chipset .

Read (Write) Mode

In Programmer interface mode, the read (write) operation of the W49V002FA is controlled by #OE

(#WE). The #OE(#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE

is the output control and is used to gate data from the output pins. The data bus is in high impedance

state when #OE is high. As for in the FWH interface mode, the read or write is determined by the "bit 0

& bit 1 of START CYCLE ". Refer to the FWH cycle definition for further details.

Reset Operation

The #RESET input pin can be used in some application. When #RESET pin is at high state, the device

is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will

be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to

read or standby mode, it depends on the control signals.

Chip Erase Operation

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading

cycle, the device enters the internal chip erase mode, which is automatically timed and will be

completed within fast 150 mS (typical). The host system is not required to provide any control or timing

during this operation. If the boot block programming lockout is activated, only the data in the other

memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains

as the same state before the chip erase operation). The entire memory array will be erased to FF(hex)

by the chip erase operation if the boot block programming lockout feature is not activated. The device

will automatically return to normal read mode after the erase operation completed. Data polling and/or

Toggle Bits can be used to detect end of erase cycle.

Sector Erase Operation

The seven sectors, one boot block and two parameter memory and four main blocks, can be erased

individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE

edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE.

After the command loading cycle, the device enters the internal sector erase mode, which is

automatically timed and will be completed within fast 150 mS (typical). The host system is not required

to provide any control or timing during this operation. The device will automatically return to normal

read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect

end of erase cycle.