W29EE011

Publication Release Date: July 1999

- 3 -

Revision A12

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29EE011 is controlled by CE and OE , both of which have to be low for

the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip

is de-selected and only standby power will be consumed. OE is the output control and is used to gate

data from the output pins. The data bus is in high impedance state when either CE or OE is high.

Refer to the timing waveforms for further details.

Page Write Mode

The W29EE011 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of

data within a page is to be changed, data for the entire page must be loaded into the device. Any byte

that is not loaded will be erased to "FFh" during programming of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists

of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device.

Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously

written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE,

whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs

µS, after the initial byte-load cycle, the W29EE011 will stay in the page load cycle. Additional bytes

can then be loaded consecutively. The page load cycle will be terminated and the internal

programming cycle will start if no additional byte is loaded into the page buffer within 300

from the last byte-load cycle, i.e., there is no subsequent WE high-to-low transition after the last

be loaded in any order; sequential loading is not required.

In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written

simultaneously into the memory array. Before the completion of the internal programming cycle, the

host is free to perform other tasks such as fetching data from other locations in the system to prepare

to write the next page.

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is

enabled, any write operation requires a series of three-byte program commands (with specific data to

a specific address) to be performed before the data load operation. The three-byte load command

sequence begins the page load cycle, without which the write operation will not be activated. This

write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by

noise during system power-up and power-down.

The W29EE011 is shipped with the software data protection enabled. To enable the software data

protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The

device will then enter the software data protection mode, and any subsequent write operation must be

preceded by the three-byte program command cycle. Once enabled, the software data protection will

remain enabled unless the disable commands are issued. A power transition will not reset the

software data protection feature. To reset the device to unprotected mode, a six-byte command

sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram.