W25P243A

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FUNCTIONAL DESCRIPTION

The W25P243A is a synchronous-burst pipelined SRAM designed for use in high-end personal

computers. It supports two burst address sequences for Intel

™ systems (Interleaved mode) and linear

mode, which can be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC

and the burst counter is incremented whenever ADV is sampled low.

BURST ADDRESS SEQUENCE

A[1:0]

A[1:0]

A[1:0]

A[1:0]

A[1:0]

A[1:0]

A[1:0]

A[1:0]

External Start Address

00

01

10

11

00

01

10

11

Second Address

01

00

11

10

01

10

11

00

Third Address

10

11

00

01

10

11

00

01

Fourth Address

11

10

01

00

11

00

01

10

The device supports several types of write mode operations. BWE and BW [8:1] support individual

byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is

used to override the byte enable signals and allows the cache controller to write all bytes to the

SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the

Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the

SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM

latches both data and valid byte enable signals from the processor.

TRUTH TABLE

CYCLE

ADDRESS

USED

CE1

CE2

CE3

ADSP

ADSC

ADV

OE

DATA

WRITE*

Unselected

No

1

X

X

X

0

X

X

Hi-Z

X

Unselected

No

0

X

1

0

X

X

X

Hi-Z

X

Unselected

No

0

0

X

0

X

X

X

Hi-Z

X

Unselected

No

0

X

1

1

0

X

X

Hi-Z

X

Unselected

No

0

0

X

1

0

X

X

Hi-Z

X

Begin Read

External

0

1

0

0

X

X

X

Hi-Z

X

Begin Read

External

0

1

0

1

0

X

X

Hi-Z

Read

Continue Read

Next

X

X

X

1

1

0

1

Hi-Z

Read

Continue Read

Next

X

X

X

1

1

0

0

D-Out

Read

Continue Read

Next

1

X

X

X

1

0

1

Hi-Z

Read

Continue Read

Next

1

X

X

X

1

0

0

D-Out

Read

Suspend Read

Current

X

X

X

1

1

1

1

Hi-Z

Read

Suspend Read

Current

X

X

X

1

1

1

0

D-Out

Read

Suspend Read

Current

1

X

X

X

1

1

1

Hi-Z

Read

Suspend Read

Current

1

X

X

X

1

1

0

D-Out

Read