Preliminary W25S243A

64K

× 64 BURST PIPELINED HIGH-SPEED

CMOS STATIC RAM

Publication Release Date: November 1998

- 1 -

Revision A1

GENERAL DESCRIPTION

The W25S243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM

organized as 65,536

× 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst

address counter supports both Pentium

™ burst mode and linear burst mode. The mode to be

executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by

the FT pin. A snooze mode can reduces power dissipation.

This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.

FEATURES

(Interleaved) mode & linear burst mode

BLOCK DIAGRAM

A(15:0)

DATA I/O

REGISTER

INPUT

REGISTER

CONTROL

LOGIC

REGISTER

64K X 64

CORE

ARRAY

CE(3:1)

BWE

CLK

OE

GW

ADSC

ADSP

ADV

LBO

BW(8:1)

I/O(64:1)

FT

ZZ