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RT9612B Datasheet(PDF) 11 Page - Richtek Technology Corporation |
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RT9612B Datasheet(HTML) 11 Page - Richtek Technology Corporation |
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11 / 15 page  RT9612A/B 11 DS9612A/B-03 June 2012 www.richtek.com © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 2. Part of Bootstrap Circuit of RT9612A/B In practice, a low value capacitor CB will lead to the over charging that could damage the IC. Therefore, to minimize the risk of overcharging and to reduce the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1 μF, and the larger the better. In general design, using 1 μF can provide better performance. At least one low-ESR capacitor should be used to provide good local de-coupling. It is recommended to adopt a ceramic or tantalum capacitor. Power Dissipation To prevent driving the IC beyond the maximum recommended operating junction temperature of 125 °C, it is necessary to calculate the power dissipation appropriately. This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 3 shows the power dissipation test circuit. CL and CU are the UGATE and LGATE load capacitors, respectively. The bootstrap capacitor value is 1 μF. Figure 3. Test Circuit Figure 4 shows the power dissipation of the RT9612A/B as a function of frequency and load capacitance. The value of CU and CL are the same and the frequency is varied from 100kHz to 1MHz. The operating junction temperature can be calculated from the power dissipation curves (Figure 4). Assume VCC = 12V, operating frequency is 200kHz and CU = CL = 1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 4, the power dissipation is 100mW. Thus, for example, with the SOP- 8 package, the package thermal resistance θJA is 120°C/ W. The operating junction temperature is then calculated as : TJ = (120 °C/W x 100mW) + 25°C = 37°C (11) where the ambient temperature is 25 °C. Thermal Considerations For recommended operating condition specifications, the maximum junction temperature is 125 °C. The junction to ambient thermal resistance, θJA, is layout dependent. For SOP-8 packages, the thermal resistance, θJA, is 120 °C/W on a standard JEDEC 51-7 four-layer thermal test board. For SOP-8 (Exposed Pad) packages, the thermal resistance, θJA, is 75°C/W on a standard JEDEC 51-7 four-layer thermal test board. For WDFN-8EL 3x3 packages, the thermal resistance, θJA, is 70°C/W on a Figure 4. Power Dissipation vs. Frequency VIN CB VCB + - BOOT VCC UGATE PHASE LGATE GND CU 3nF VCC PWN GND BOOT UGATE PHASE LGATE RT9612A/B 1µF CL 3nF 20 2N7002 2N7002 12V 12V 1µF PWM CBOOT 10 Power Dissipation vs. Frequency 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 Frequency (kHz) CU = CL = 1nF CU = CL = 3nF CU = CL = 2nF |
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