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RT6030 Datasheet(PDF) 9 Page - Richtek Technology Corporation |
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RT6030 Datasheet(HTML) 9 Page - Richtek Technology Corporation |
9 / 10 page 9 RT6030 DS6030-02 March 2011 www.richtek.com PD(MAX) = (125 °C − 25°C) / (95°C/W) = 1.053W for SOP-16 package The maximum power dissipation depends on the operating ambient temperature for fixed TJ(MAX) and thermal resistance, θJA. For the RT6030 package, the derating curve in Figure 1 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Figure 1. Derating Curve for RT6030 Package Layout Considerations There are three critical layout considerations. First the current setting resistor should be placed as close as possible to the RT6030 to prevent any noise coupling. Second of all CIN and COUT should be placed near the RT6030 for good performance. Last of all, proper copper area for the pass element should be acknowledged. Pass elements operating under high power situations can result in abnormally junction temperature. In addition to the package thermal resistance limit, the copper area should be increased accordingly to improve the power dissipation. VCC12 EN2 FB2 DRI2 EN4 GND FB4 DRI1 FB1 GND EN1 FB3 DRI3 EN3 DRI4 VCC34 6 7 8 4 5 2 3 16 13 15 14 12 9 11 10 GND RDRI3 R3 VCC C12 VLED RDRI1 R1 R2 RDRI2 VCC GND RDRI4 R4 C34 The GND plane should be connected to a strong ground plane for heat sinking and noise protection. CIN should be placed near the IC for improve performance. FBx node copper area should be minimized and kept far away from noise sources. VLED VLED VLED Figure 2. PCB Layout Guide 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 025 50 75 100 125 Ambient Temperature (°C) Single-Layer PCB |
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