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FSQ0270RNA Datasheet(PDF) 9 Page - Fairchild Semiconductor |
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FSQ0270RNA Datasheet(HTML) 9 Page - Fairchild Semiconductor |
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9 / 17 page  © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0170RNA, FSQ0270RNA Rev. 1.0.5 9 Functional Description 1. Startup: In previous generations of Fairchild Power Switches (FPS™), the Vstr pin required an external resistor to the DC input voltage line. In this generation, the startup resistor is replaced by an internal high- voltage current source and a switch that shuts off 10ms after the supply voltage, VCC, goes above 12V. The source turns back on if VCC drops below 8V. Figure 13. High-Voltage Current Source 2. Feedback Control: The 700V FPS series employs current-mode control, as shown in Figure 14. An opto- coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor of SenseFET, plus an offset voltage, makes it possible to control the switching duty cycle. When the shunt regulator reference pin voltage exceeds the internal reference voltage of 2.5V, the opto-coupler LED current increases, the feedback voltage VFB is pulled down and thereby reduces the duty cycle. This typically happens when the input voltage increases or the output load decreases. Figure 14. Pulse Width Modulation Circuit 3. Leading Edge Blanking (LEB): When the internal SenseFET is turned on, the primary-side capacitance and secondary-side rectifier diode reverse recovery typically cause a high-current spike through the SenseFET. Excessive voltage across the Rsense resistor leads to incorrect feedback operation in the current- mode PWM control. To counter this effect, the FPS employs a Leading Edge Blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (tLEB) after the Sense FET is turned on. 4. Protection Circuits: The FPS has several protective functions, such as Overload Protection (OLP), Over- Voltage Protection (OVP), Under-Voltage Lockout (UVLO), and Thermal Shutdown (TSD). Because these protection circuits are fully integrated in the IC without external components, reliability is improved without increasing cost. Once a fault condition occurs, switching is terminated and the SenseFET remains off. This causes VCC to fall. When VCC reaches the UVLO stop voltage, VSTOP (typically 8V), the protection is reset and the internal high-voltage current source charges the VCC capacitor via the Vstr pin. When VCC reaches the UVLO start voltage, VSTART (typically 12V), the FPS resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated. 4.1 Overload Protection (OLP): Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated to protect the SMPS. However, even when the SMPS is operating normally, the OLP circuit can be activated during the load transition. To avoid this undesired operation, the OLP circuit is designed to be activated after a specified time to determine whether it is a transient situation or a true overload situation. In conjunction with the IPK current limit pin (if used), the current mode feedback path limits the current in the SenseFET when the maximum PWM duty cycle is attained. If the output consumes more than this maximum power, the output voltage (VO) decreases below nominal voltage. This reduces the current through the opto-coupler LED, which also reduces the opto- coupler transistor current, thus increasing the feedback voltage (VFB). If VFB exceeds 3V, the feedback input diode is blocked and the 5µA current source (IDELAY) starts to slowly charge CFB up to VCC. In this condition, VFB increases until it reaches 6V, when the switching operation is terminated, as shown in Figure 15. The shutdown delay time is the time required to charge CFB from 3V to 6V with 5µA current source. Figure 15. Overload Protection (OLP) 4.2 Thermal Shutdown (TSD): The SenseFET and the control IC are integrated, making it easier for the control V IN,dc V str V cc 10ms after V cc ≥12V UVLO off V cc<8V UVLO on I STR J-FET I CH FSQ0x70RNA Rev. 1.00 3 OSC V CC 5 A 900 A V SD R 2.5R Gate driver OLP D1 D2 V FB 431 C FB V O + - V FB,in V CC FSQ0x70RNA Rev. 1.00 FB 21 12 1 2 () ( ) ; 5 , ( )3 , ( )6 FB DELAY DELAY Vt V t t C I A Vt VV t V I V FB t 3V 6V Overload Protection t 12= CFB ×(V(t 2)-V(t1)) / IDELAY t 1 t 2 FSQ0x70RNA Rev.00 |
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