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LV8121V Datasheet(PDF) 6 Page - Sanyo Semicon Device |
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LV8121V Datasheet(HTML) 6 Page - Sanyo Semicon Device |
6 / 14 page LV8121V No.A2135-6/14 Pin Function Pin No. Pin name Function Equivalent circuit 1 PWM Pin to set the PWM oscillation frequency. Connect a capacitor between this pin and GND1. A frequency of about 19kHz can be set by using a 1800pF capacitor. VREG 1 950 Ω 200 Ω 2 LIM Pin to set the minimum output duty. A minimum output duty can be set by inputting a fixed voltage to the LIM pin through resistor division of VREG. Connect the LIM pin to GND1 if this pin is not used, then the minimum output duty becomes 0 %. VREG 2 500 Ω 3 CTL Pin to control the output duty. The output duty is determined by the result of comparing the CTL pin voltage with the PWM oscillation waveform. When the CTL pin is open, the output duty becomes 100%. Therefore, connect a pull-down resistor to prevent open. VREG 3 500 Ω 4 S/S Start / Stop control pin. Low : 0V to 1.0V High : 2.0V to VREG Goes high when left open. Low for start. The hysteresis width is about 0.35V. 10k Ω VREG 4 100k Ω 5 6 7 8 9 10 IN3- IN3+ IN2- IN2+ IN1- IN1+ Hall input pins. The input is seen as the high level input when IN+ > IN-, and as the low level input for the opposite state. If noise on the Hall signals is a problem, connect a capacitor between the corresponding IN+ and IN- inputs. VREG 8 6 10 7 5 9 Continued on next page. |
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