STK672-732B-E

No. A1931-5/23

Sample Application Circuit

Precautions

[GND wiring]

• To reduce noise on the 5V system, be sure to place the GND of C01 in the circuit given above as close as possible to

Pin 2 and Pin 6 of the hybrid IC. Also, to achieve accurate current settings, be sure to connect Vref GND to the point

where P.G1 and P.G2 share a connection.

[Input pins]

• If VDD is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to P.GND, and

do not apply a voltage greater than or equal to VDD voltage.

• Do not wire by connecting the circuit pattern on the P.C.B side to Pin 4, 11, or 18 on the N.C. shown in the internal

block diagram.

• Apply 2.5V high level input to pins 13, 17, 12, 10, 14, and 15.

• Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 13, 17, 12, 10, 14, and 15

are used as inputs, a 1 to 20k

Ω pull-up resistor (to VDD) must be used.

At this time, use a device for the open collector driver that has output current specifications that pull the voltage down

to less than 0.8V at Low level (less than 0.8V at Low level when IOL=5mA).

[Current setting Vref]

If the motor current is temporarily reduced, the circuit given below (STK672-732B-E : IOH>0.2A) is recommended.

5V

R01

R02

R3

5V

R01

R02

R3

Vref

Vref

+

9

13

17

12

10

15

14

16

19

18

6

2

7

5

1

3

VDD(5V)

φA

φAB

φB

ENABLE

RESETB

FAULT1

A

AB

B

BB

Vref

R01

R03

R02

N.C

P.G1

P.G2

VCC

24V

C01

at least 100

μF

2 phase stepping motor driver

8

FAULT2

φBB

P.GND

STK672-732B-E