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ICX412AQF Datasheet(PDF) 4 Page - Sony Corporation |
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ICX412AQF Datasheet(HTML) 4 Page - Sony Corporation |
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4 / 30 page  – 4 – ICX412AQF Bias Conditions Supply voltage Protective transistor bias Substrate clock Reset gate clock Item VDD VL φSUB φRG Symbol 15.0 ∗1 ∗2 ∗2 Min. V Unit Remarks Typ. Max. ∗1 V L setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD. DC Characteristics 14.55 15.45 Supply current Item IDD Symbol 7.5 Min. Unit Remarks Typ. Max. mA 9.5 5.5 Clock Voltage Conditions Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Reset gate clock voltage Substrate clock voltage Item VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 V φV VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL V φH VHL VCR V φRG VRGLH – VRGLL VRGL – VRGLm V φSUB Symbol 14.55 –0.05 –0.2 –8.0 6.8 –0.25 –0.25 4.0 –0.05 0.8 3.0 21.5 Min. 15.0 0 0 –7.5 7.5 5.0 0 2.5 3.3 22.5 Typ. 15.45 0.05 0.05 –7.0 8.05 0.1 0.1 0.8 0.9 0.9 0.8 5.25 0.05 5.25 0.4 0.5 23.5 Max. Unit 1 2 2 2 2 2 2 2 2 2 2 3 3 3 4 4 4 5 Waveform Diagram VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 V φV = VVHn – VVLn (n = 1 to 4) High-level coupling High-level coupling Low-level coupling Low-level coupling Cross-point voltage Low-level coupling Low-level coupling Remarks V V V V V V V V V V V V V V V V V V |
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