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MPXS3020VMS2R Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc

Part # MPXS3020VMS2R
Description  PXS30 Microcontroller
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPXS3020VMS2R Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc

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PXS30 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Introduction
Freescale Semiconductor
8
Floating point
—IEEE
 754 compatible with software wrapper
— Single precision in hardware; double precision with software library
— Conversion instructions between single precision floating point and fixed point
Long cycle time instructions (except for guarded loads) do not increase interrupt latency in the
PXS30
To reduce latency, long cycle time instructions are aborted upon interrupt requests
Extensive system development support through Nexus debug module
1.5.2
Crossbar switch (XBAR)
32-bit address bus, 64-bit data bus
Simultaneous accesses from different masters to different slaves (there is no clock penalty when a
parked master accesses a slave)
1.5.3
Memory Protection Unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each master (DMA,
FlexRay, CPU) can be assigned different access rights to each region.
16-region MPU with concurrent checks against each master access
32-byte granularity for protected address region
1.5.4
Enhanced Direct Memory Access (eDMA) controller
32 channels support independent 8-, 16-, 32-bit single value or block transfers
Supports variable-sized queues and circular queues
Source and destination address registers are independently configured to post-increment or remain
constant
Each transfer is initiated by a peripheral, CPU, or eDMA channel request
Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single
value or block transfer
1.5.5
Interrupt Controller (INTC)
208 peripheral interrupt requests
8 software settable sources
Unique 9-bit vector per interrupt source
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Priority elevation for shared resources


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