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ICX278AK Datasheet(PDF) 6 Page - Sony Corporation |
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ICX278AK Datasheet(HTML) 6 Page - Sony Corporation |
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6 / 19 page  – 6 – ICX278AK (3) Horizontal transfer clock waveform (4) Reset gate clock waveform VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: V φRG = VRGH – VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% 10% 0% VSUB (A bias generated within the CCD) tr tf twh φM 2 φM V φSUB tr twh tf 90% 10% twl V φH VHL Point A twl V φRG VRGH VRGL VRGLH RG waveform VRGLL H φ1 waveform twh tr tf V φH/2 [V] VRGLm |
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