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MPXN2005VLU120R Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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MPXN2005VLU120R Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 130 page  Overview PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor 7 — 208 LQFP, 0.5 mm pitch, 28 mm 28 mm outline — 416 TEPBGA, 1mm ball pitch, 27 mm 27 mm outline 1.4 Feature details 1.4.1 Low-power operation The PXD20 is designed for optimized low-power operation and dynamic power management of the CPU and peripherals. Power management features include software-controlled clock gating of peripherals and multiple power domains to minimize leakage in low-power modes. There are three low-power modes: • STANDBY •STOP • HALT and five dynamic power modes — RUN[0..3] and DRUN. All low-power modes use clock gating to halt the clock for all or part of the device. STANDBY mode turns off the power to the majority of the chip to offer the lowest power consumption mode. The device can be awakened from STANDBY mode via from any of up to 23 I/O pins, a reset or from a periodic wake-up using a low power oscillator. If required, it is possible to enable the internal 16 MHz oscillator, the external 4–16 MHz oscillator and the external 32 KHz oscillator. In STANDBY mode the contents of the CPU, on-chip peripheral registers and potentially some of the volatile memory are lost. The two possible configurations in STANDBY mode are: • The device retains 64 KB of the on-chip SRAM, but the content of the graphics SRAM is lost. • The device retains 8 KB of the on-chip SRAM, but the content of the graphics SRAM is lost. STOP mode maintains power to the entire device allowing the retention of all on-chip registers and memory, and providing a faster recovery low power mode than the lowest-power STANDBY mode. There is no need to reconfigure the device before executing code. The clocks to the CPU and peripherals are halted and can be optionally stopped to the oscillator or PLL at the expense of a slower start-up time. STOP is entered from RUN mode only. Wake-up from STOP mode is triggered by an external event or by the internal periodic wake-up, if enabled. RUN modes are the main operating modes where the entire device can be powered and clocked and from which most processing activity is done. Four dynamic RUN modes are supported—RUN0 - RUN3. The ability to configure and select different RUN modes enables different clocks and power configurations to be supported with respect to each other and to allow switching between different operating conditions. The necessary peripherals, clock sources, clock speed and system clock prescalers can be independently configured for each of the four RUN modes of the device. HALT mode is a reduced activity, low power mode intended for moderate periods of lower processing activity. In this mode the CPU system clocks are stopped but user-selected peripheral tasks can continue to run. It can be configured to provide more efficient power management features (switch-off PLL, flash memory, main regulator, etc.) at the cost of longer wake up latency. The system returns to RUN mode as soon as an event or interrupt is pending. Table 2 summarizes the operating modes of the PXD20. |
Similar Part No. - MPXN2005VLU120R |
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Similar Description - MPXN2005VLU120R |
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