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EN6337QI Datasheet(PDF) 2 Page - Enpirion, Inc. |
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EN6337QI Datasheet(HTML) 2 Page - Enpirion, Inc. |
2 / 17 page 05800 6/17/2011 Rev: B EN6337QI ©Enpirion 2011 all rights reserved, E&OE 2 www.enpirion.com Figure 2: Typical Application Schematic (PWM mode) Ordering Information Part Number Temp Rating (°C) Package EN6337QI -40 to +85 38-pin QFN T&R EN6337QI3 -40 to +85 38-pin QFN T&R EN6337QI-E QFN Evaluation Board Pin Assignments (Top View) Figure 3: Top View Pinout Diagram (Not to Scale) NOTE: All perimeter pins must be soldered to PCB. Pin Description PIN NAME FUNCTION 1-2, 12, 34-38 NC(SW) NO CONNECT – These pins are internally connected to the common switching node of the internal MOSFETs. They are not to be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may result in damage to the device. 3-4, 22-25 NC NO CONNECT – These pins may be internally connected. Do not connect to each other or to any other electrical signal. Failure to follow this guideline may result in device damage. 5-11 VOUT Regulated converter output. Connect these pins to the load and place output capacitor between these pins and PGND pins 13-15. 13-18 PGND Input/Output power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See VOUT and PVIN pin descriptions for more details. 19-21 PVIN Input power supply. Connect to input power supply. Decouple with input capacitor to PGND pins 16-18. 26 LLM/SYNC Dual function pin providing LLM Enable and External Clock Synchronization (see Application Section). At static Logic HIGH, device will allow automatic engagement of light load mode. At static logic LOW, the device is forced into PWM only. A clocked input to this pin will synchronize the internal switching frequency to the external signal. If this pin is left floating, it will pull to a static logic high, enabling LLM. 27 ENABLE Input Enable. Applying logic high enables the output and initiates a soft-start. Applying logic low disables the output. 28 POK Power OK is an open drain transistor used for power system state indication. POK is logic high when VOUT is within -10% of VOUT nominal. 29 RLLM Programmable LLM engage resistor to AGND allows for adjustment of load current at which Light-Load Mode engages. Can be left open for PWM only operation. 30 SS Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The value of this capacitor determines the startup time. 31 VFB External Feedback Input. The feedback loop is closed through this pin. A voltage divider at VOUT is used to set the output voltage. The midpoint of the divider is connected to VFB. A phase lead capacitor from this pin to VOUT is also required to stabilize the loop. 32 AGND Analog Ground. This is the controller ground return. Connect to a quiet ground. 33 AVIN Input power supply for the controller. Connect to input voltage at a quiet point. 39 PGND Device thermal pad to be connected to the system GND plane. See Layout Recommendations section. |
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