Features

PXN20 Product Brief, Rev. 1

Freescale Semiconductor

7

– In Sleep mode the 32 kHz XTAL can be enabled to run and may be selected to clock the

RTC and API

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Up to 32 external pins for wake-up from low power modes

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Input filters available on all wake-up pins to minimize false wakeups due to noise

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Rapid exit from low power mode with fast startup internal voltage regulator

2.5

Packages

PXN20 family members are offered in the following package types:

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208-ball MAPBGA, 1mm ball pitch, 17mm

 17mm outline for production

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256-ball MAPBGA 1mm ball pitch 17mm

 17mm outline for emulation, providing access to full

Nexus port without sacrificing GPIO functionality (not available for production)

2.6

Module Features

The following sections provide details of the modules implemented on the PXN20 family.

2.6.1

High Performance e200z650 Core Processor (CPU)

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Freescale Variable Length Encoding (VLE) enhancements for code size footprint reduction

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Thirty-two 64-bit general-purpose registers (GPRs)

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Memory management unit (MMU) with 32-entry fully-associative translation look-aside buffer

(TLB)

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Branch processing unit

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Fully pipelined load/store unit

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32 KB unified cache with line locking

— 4/8-way set associative

— Two 32-bit fetches per clock

— Eight-entry store buffer

— Way locking

— Supports assigning cache as instruction or data only on a per way basis

— Supports tag and data parity

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Vectored interrupt support

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Very low interrupt latency

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Reservation instructions for implementing read-modify-write constructs (internal SRAM and

flash)

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Signal processing engine (SPE) auxiliary processing unit (APU) operating on 64-bit general

purpose registers

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Floating point