PXN20 Product Brief, Rev. 1

Features

Freescale Semiconductor

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— Single precision in hardware; double precision with software library

— Conversion instructions between single precision floating point and fixed point

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Wait instruction

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Extensive system development support through Nexus debug module

2.6.2

I/O Processor High Performance e200z0 Core (IOP)

The IOP supports the following features:

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High performance, low cost e200z0 core processor for managing peripherals and interrupts

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Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions

— Results in efficient code size footprint

— Minimizes impact on performance

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Branch processing acceleration using lookahead instruction buffer

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Load/store unit

— 1-cycle load latency

— Misaligned access support

— No load-to-use pipeline bubbles

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Thirty-two 32-bit general purpose registers (GPRs)

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Hardware vectored interrupt support

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Reservation instructions for implementing read-modify-write constructs

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Multi-cycle divide (divw) and load multiple (lmw) store multiple (smw) multiple class

instructions, can be interrupted to prevent increases in interrupt latency

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Extensive system development support through Nexus debug port

2.6.3

On-Chip Flash

On-chip flash on the PXN20 devices features the following:

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2 MB burst flash memory

— Flash partitioning: 4

 16 KB; 4  16 KB; 2  64 KB; 2  128 KB; 6  256 KB

— 16 KB shadow flash blocks

— Typical flash access time: 0 wait-state for buffer hits, 3 wait-states for page buffer miss at

116 MHz

— 64-bit ECC with single-bit correction, double-bit detection for data integrity

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Dual flash ports to minimize access contention between main core and IOP

— Each port supported with separate page buffers

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Flash page buffers to improve access time to code and data held in flash

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 128-bit page buffers with programmable prefetch control for flash access