 |
 |
|
| ICX248AK |
|
|||||||||||||||||
 SONY
|
| |||||||||||||||||
|
5 page 
– 5 – ICX248AK Item Readout clock voltage VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 V φV | VVH1 – VVH2 | VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL V φH VHL VRGL V φRG VRGLH – VRGLL V φSUB 14.55 –0.05 –0.2 –9.6 8.3 –0.25 –0.25 4.75 –0.05 4.5 23.0 15.0 0 0 –9.0 9.0 5.0 0 ∗1 5.0 24.0 15.45 0.05 0.05 –8.5 9.65 0.1 0.1 0.1 0.5 0.5 0.5 0.5 5.25 0.05 5.5 0.8 25.0 V V V V Vp-p V V V V V V V Vp-p V V Vp-p V V 1 2 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 V φV = VVHn – VVLn (n = 1 to 4) High-level coupling High-level coupling Low-level coupling Low-level coupling Low-level coupling Horizontal transfer clock voltage Reset gate clock voltage∗1 Substrate clock voltage Vertical transfer clock voltage Symbol Min. Typ. Max. Unit Waveform diagram Remarks Item Symbol Min. Typ. Max. Unit Waveform diagram Remarks ∗1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven with the following specifications. Reset gate clock voltage VRGL V φRG –0.2 8.5 0 9.0 0.2 9.5 V Vp-p 4 4 Clock Voltage Conditions |
