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F28M35H32B1RFPT Datasheet(PDF) 5 Page - Texas Instruments |
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F28M35H32B1RFPT Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 192 page  F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data sheet revision history highlights the technical changes made to the SPRS742C device-specific data sheet to make it an SPRS742D revision. Scope: Added new sections. See table below. LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS Section 1.1 Features: • Changed "Up to 72 Individually Programmable, Multiplexed GPIO Pins" to "Up to 74 Individually Programmable, Multiplexed GPIO Pins" – Added "Glitch-free I/Os" feature • Control Subsystem — TMS320C28x™ 32-Bit CPU: – Added "External Peripheral Interface (EPI)" feature • Analog Subsystem: – Removed "On-chip Temperature Sensor" Figure 1-1 Updated Functional Block Diagram Table 2-1 Hardware Features: • 12-Bit ADC 1: – Removed "Temperature Sensor" • Updated "Voltage Regulator and Monitor" • Updated "Clocking" Table 2-3 Control Subsystem Peripheral Frame 0 (Includes Analog): • 0000 1780 – 0000 17FF: Added C Hardware Logic BIST Registers Table 2-8 Control Subsystem Flash, ECC, OTP, Boot ROM: • Added "M Address (Byte-Aligned)" column • Added "µDMA Access" column • 0030 0000 – 003F 7FFF: Added EPI0 • 003F 8000 – 003F FFFF: Added C28x Boot ROM • Added "The letter "M" refers to the Master Subsystem" footnote • Added "The Control Subsystem has no direct access to EPI in silicon revision 0 devices" footnote Table 2-12 Master Subsystem Analog and EPI: • Added "C Address (x16 Aligned)" column • Added "C DMA Access" column • 6000 0000 – DFFF FFFF: Updated the above two new columns • Added "The letter "C" refers to the Control Subsystem" footnote • Added "The Control Subsystem has no direct access to EPI in silicon revision 0 devices" footnote Section 2.3 Master Subsystem: • Updated "The Master Subsystem includes ..." paragraph Section 2.3.1 Cortex™-M3 CPU: • Removed "MPU is not available on silicon revision 0 devices" NOTE Section 2.3.2 Added "Cortex™-M3 Core Hardware Logic Built-In Test (LBIST)" section Figure 2-1 Updated "Master Subsystem" figure Table 2-14 Interrupts from NVIC to Cortex™-M3: • Interrupt Number: Changed 91 to "91–133". Updated "Vector Number" column. Updated "Vector Address or Offset" column. Section 2.3.6 Cortex™-M3 Local Peripherals: • Updated "The Cortex™-M3 local peripherals include two Watchdogs ..." paragraph Section 2.3.8 Cortex™-M3 Accessing Shared Resources and Analog Peripherals: • Updated "There are several memories ..." paragraph • Updated "The Shared Resources ..." paragraph • Updated "The Analog Subsystem has ADC1 ..." paragraph Copyright © 2011–2012, Texas Instruments Incorporated Contents 5 Submit Documentation Feedback |
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