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F28M35H22C1RFPT Datasheet(PDF) 7 Page - Texas Instruments |
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F28M35H22C1RFPT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 192 page  F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 www.ti.com SPRS742D – JUNE 2011 – REVISED AUGUST 2012 LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS Section 2.16.1 GPIO_MUX1: • Updated " ... pins of the GPIO_MUX1 block can be selectively mapped ..." paragraph • Updated "Pin-Level Mux assigns Master Subsystem peripheral signals ..." paragraph • Updated "The configuration registers for the muxing of Master Subsystem peripherals ..." paragraph • Updated "In addition to passing mostly digital signals ..." paragraph • Added NOTE about GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46 Figure 2-13 Updated "GPIOs and Other Pins" figure Figure 2-14 Updated "GPIO_MUX1 Block" figure Figure 2-15 Updated "GPIO_MUX1 Pin Mapping Through Register Set A" figure Table 2-27 GPIO_MUX1 Pin Assignments (M3 Primary Modes): • PB6_GPIO14: Updated "M3 Primary Mode 8" column • PB7_GPIO15: Updated "M3 Primary Mode 8" column • PE4_GPIO28: Updated "M3 Primary Mode 8" column • PE5_GPIO29: Updated "M3 Primary Mode 8" column • PF2_GPIO34: Updated "M3 Primary Mode 8" column • PF3_GPIO35: Updated "M3 Primary Mode 8" column • PF6_GPIO38: – Updated "M3 Primary Mode 1" column – Updated "M3 Primary Mode 3" column – Updated "M3 Primary Mode 8" column – Updated "M3 Primary Mode 10" column • PG2_GPIO42: Updated "M3 Primary Mode 8" column • PG5_GPIO45: Updated "M3 Primary Mode 8" column • PG6_GPIO46: – Updated "M3 Primary Mode 3" column – Updated "M3 Primary Mode 8" column – Updated "M3 Primary Mode 10" column • Added footnote about muxing option availability Table 2-28 GPIO_MUX1 Pin Assignments (M3 Alternate Modes): • PA6_GPIO6: Updated "M3 Alternate Mode 12" column • PE4_GPIO28: Updated "M3 Alternate Mode 14" column • Added footnote about muxing option availability Table 2-29 GPIO_MUX1 Pin Assignments (C28x Peripheral Modes): • PF6_GPIO38: Updated "C28x Peripheral Mode 0" column • PG6_GPIO46: Updated "C28x Peripheral Mode 0" column Section 2.16.2 GPIO_MUX2: • Updated "Peripheral Modes 0, 1, 2, and 3 are chosen ..." paragraph Table 2-30 Updated "GPIO_MUX2 Pin Assignments (C28x Peripheral Modes)" table Figure 2-16 Updated "Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2" figure Section 2.17 Added "Emulation/JTAG" section Section 2.18 Added "Code Security Module (CSM)" section Section 2.19 Added "µCRC Module" section Figure 3-1 144-Pin RFP PowerPAD™ HTQFP (Top View): • Pin 109: Changed signal name from "GPIO199/COMP5OUT" to "GPIO135/COMP5OUT" • Pin 110: Changed signal name from "GPIO198" to "GPIO134" • Pin 111: Changed signal name from "GPIO197/COMP4OUT" to "GPIO133/COMP4OUT" • Pin 112: Changed signal name from "GPIO196/COMP3OUT" to "GPIO132/COMP3OUT" • Pin 118: Changed signal name from "ADC1VREFLO, VSSA1" to "VSSA1" • Pin 135: Changed signal name from "ADC2VREFLO, VSSA2" to "VSSA2" • Pin 140: Changed signal name from "GPIO192" to "GPIO128" • Pin 141: Changed signal name from "GPIO193/COMP1OUT" to "GPIO129/COMP1OUT" • Pin 142: Changed signal name from "GPIO194/COMP6OUT" to "GPIO130/COMP6OUT" • Pin 143: Changed signal name from "GPIO195/COMP2OUT" to "GPIO131/COMP2OUT" • Added footnote about GPIO135 Copyright © 2011–2012, Texas Instruments Incorporated Contents 7 Submit Documentation Feedback |
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