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ICX074 Datasheet(PDF) 10 Page - Sony Corporation |
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ICX074 Datasheet(HTML) 10 Page - Sony Corporation |
10 / 21 page – 10 – ICX074AK Readout clock Vertical transfer clock During imaging During parallel- serial conversion Reset gate clock Substrate clock Vertical final stage accumulation/ transfer clock Inter-horizontal register transfer clock VT V φ1, V φ2, Vφ3 H φ1 H φ2 H φ1 H φ2 φRG φSUB VHOLD φ VOG φ HHG φ1 HHG φ2 2.3 24 26 11 1.6 2.5 29 31 13 1.9 26 24 31 29 64 0.5 10 10 0.01 0.01 2 20 20 20 20 17.5 15 0.5 15 0.5 10 10 0.01 0.01 2 20 20 20 20 350 17.5 15 0.5 µs ns ns µs ns µs ns ns ns ns During readout ∗1 ∗2 During drain charge Item Symbol twh twl tr tf, tf1, tf2 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Remarks Horizontal transfer clock H φ1, Hφ2 24 29 ns ∗3 Item Symbol two Min. Typ. Max. Unit Remarks ∗1 When vertical transfer clock driver CXD1268M is used. ∗2 tf ≥ tr – 2ns, and the cross-point voltage (V CR ) for the H φ1 rising side of the Hφ1 and Hφ2 waveforms must be at least 2.5V. ∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ 1 and H φ2 is two. Clock Switching Characteristics |
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