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IS46R16160D-6BLA2 Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS46R16160D-6BLA2 Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
1 / 32 page Integrated Silicon Solution, Inc. 1 Rev. B 06/19/2012 Copyright©2012IntegratedSiliconSolution,Inc.Allrightsreserved.ISSIreservestherighttomakechangestothisspecificationanditsproductsatanytimewithout notice.ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.Customersareadvisedtoobtainthelat- estversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts. IntegratedSiliconSolution,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcanreason- ablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.Productsarenotauthorizedforuseinsuchapplications unlessIntegratedSiliconSolution,Inc.receiveswrittenassurancetoitssatisfaction,that: a.)theriskofinjuryordamagehasbeenminimized; b.)theuserassumeallsuchrisks;and c.)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances IS43R83200D IS43/46R16160D, IS43/46R32800D FEATURES • VDDandVDDQ:2.5V±0.2V • SSTL_2compatibleI/O • Double-dataratearchitecture;twodatatransfers perclockcycle • Bidirectional,datastrobe(DQS)istransmitted/ receivedwithdata,tobeusedincapturingdata atthereceiver • DQSisedge-alignedwithdataforREADsand centre-alignedwithdataforWRITEs • Differentialclockinputs(CKandCK) • DLLalignsDQandDQStransitionswithCK transitions • CommandsenteredoneachpositiveCKedge;data anddatamaskreferencedtobothedgesofDQS • Fourinternalbanksforconcurrentoperation • DataMaskforwritedata.DMmaskswritedata atbothrisingandfallingedgesofdatastrobe • BurstLength:2,4and8 • BurstType:SequentialandInterleavemode • ProgrammableCASlatency:2,2.5and3 • AutoRefreshandSelfRefreshModes • AutoPrecharge • TRASLockoutsupported(tRAP=tRCD) OPTIONS • Configuration(s):8Mx32,16Mx16,32Mx8 • Package(s): 144BallBGA(x32) 66-pinTSOP-II(x8,x16)and60BallBGA(x8,x16) • Lead-freepackageavailable • TemperatureRange: Commercial(0°Cto+70°C) Industrial(-40°Cto+85°C) Automotive,A1(-40°Cto+85°C) Automotive,A2(-40°Cto+105°C) 8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM JUNE 2012 DEVICE OVERVIEW ISSI’s256-MbitDDRSDRAMachieveshighspeeddata transferusingpipelinearchitectureandtwodataword accessesperclockcycle.The268,435,456-bitmemory arrayisinternallyorganizedasfourbanksof64Mbto allowconcurrentoperations.ThepipelineallowsRead andWriteburstaccessestobevirtuallycontinuous,with theoptiontoconcatenateortruncatethebursts.The programmablefeaturesofburstlength,burstsequence andCASlatencyenablefurtheradvantages.Thedevice isavailablein8-bit,16-bitand32-bitdatawordsize InputdataisregisteredontheI/Opinsonbothedges ofDataStrobesignal(s),whileoutputdataisreferenced tobothedgesofDataStrobeandbothedgesofCLK. CommandsareregisteredonthepositiveedgesofCLK. AnAutoRefreshmodeisprovided,alongwithaSelf Refreshmode.AllI/OsareSSTL_2compatible. KEY TIMING PARAMETERS Speed Grade -5 -6 Units FCkMaxCL=3 200 167 MHz FCkMaxCL=2.5 200 167 MHz FCkMaxCL=2 133 133 MHz ADDRESS TABLE Parameter 8M x 32 16M x 16 32M x 8 Configuration 2Mx32x4 banks 4Mx16x4 banks 8Mx8x4 banks BankAddress Pins BA0,BA1 BA0,BA1 BA0,BA1 Autoprecharge Pins A8/AP A10/AP A10/AP RowAddress 4K(A0–A11) 8K(A0–A12) 8K(A0–A12) Column Address 512(A0–A7, A9) 512(A0–A8) 1K(A0–A9) RefreshCount Com./Ind./A1 A2 4K/64ms 4K/16ms 8K/64ms 8K/16ms 8K/64ms |
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