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| ICX055BK |
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– 2 – ICX055BK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note Note) : Photo sensor Horizontal register Cy Ye Cy Ye Mg G Mg G Cy Ye Cy Ye G Mg G Mg Cy Ye Cy Ye Mg G Mg G Substrate voltage SUB – GND VDD, VOUT, VSS – GND Supply voltage VDD, VOUT, VSS – SUB V φ1, Vφ2, Vφ3, Vφ4 – GND Vertical clock input voltage V φ1, Vφ2, Vφ3, Vφ4 – SUB Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H φ1, Hφ2 – Vφ4 H φ1, Hφ2, RG, VGG – GND H φ1, Hφ2, RG, VGG – SUB VL – SUB V φ1, Vφ2, Vφ3, Vφ4, VDD, VOUT – VL RG – VL VGG, Vss, H φ1, Hφ2 – VL Storage temperature Operating temperature Pin No. Symbol Description Pin No. Symbol Description 1 2 3 4 5 6 7 8 V φ4 V φ3 V φ2 V φ1 GND VGG VSS VOUT Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Output amplifier gate bias Output amplifier source Signal output 9 10 11 12 13 14 15 16 VDD GND SUB VL RG NC H φ1 H φ2 Output amplifier drain supply GND Substrate (Overflow drain) Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock Pin Description Item –0.3 to +55 –0.3 to +18 –55 to +10 –15 to +20 to +10 to +15 to +17 –17 to +17 –10 to +15 –55 to +10 –65 to +0.3 –0.3 to +30 –0.3 to +24 –0.3 to +20 –30 to +80 –10 to +60 V V V V V V V V V V V V V V °C °C ∗1 Ratings Unit Remarks Absolute Maximum Ratings *1 +27V (Max.) when clock width<10µs, clock duty factor<0.1%. Block Diagram and Pin Configuration (Top View) |
