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MT-023 Datasheet(PDF) 1 Page - Analog Devices |
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MT-023 Datasheet(HTML) 1 Page - Analog Devices |
1 / 11 page MT-023 TUTORIAL ADC Architectures IV: Sigma-Delta ADC Advanced Concepts and Applications by Walt Kester INTRODUCTION Tutorial MT-022 discussed the basics of Σ-Δ ADCs. In this tutorial, we will look at some of the more advanced concepts including idle tones, multi-bit Σ- Δ, MASH, bandpass Σ-Δ, as well as some example applications. IDLE TONE CONSIDERATIONS In our discussion of Σ-Δ ADCs up to this point, we have made the assumption that the quantization noise produced by the Σ-Δ modulator (see Figure 1) is random and uncorrelated with the input signal. Unfortunately, this is not entirely the case, especially for the first-order modulator. Consider the case where we are averaging 16 samples of the modulator output in a 4- bit Σ-Δ ADC. ∑ ∫ + _ +VREF –VREF DIGITAL FILTER AND DECIMATOR + _ CLOCK Kfs VIN N-BITS fs fs A B 1-BIT DATA STREAM 1-BIT DAC LATCHED COMPARATOR (1-BIT ADC) 1-BIT, K fs SIGMA-DELTA MODULATOR INTEGRATOR Figure 1: First-Order Sigma-Delta ADC Figure 2 shows the bit pattern for two input signal conditions: an input signal having the value 8/16, and an input signal having the value 9/16. In the case of the 9/16 signal, the modulator output bit pattern has an extra "1" every 16th output. This will produce energy at Kfs/16, which translates into an unwanted tone. If the oversampling ratio (K) is less than 8, this tone will fall Rev.A, 10/08, WK Page 1 of 11 |
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