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SMH4802 Datasheet(PDF) 2 Page - Summit Microelectronics, Inc. |
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SMH4802 Datasheet(HTML) 2 Page - Summit Microelectronics, Inc. |
2 / 19 page 2 SMH4802 2062 2. 4 03/27/09 SUMMIT MICROELECTRONICS, Inc. Preliminary Information FUNCTIONAL BLOCK DIAGRAM The SMH4802 is an integrated power controller for hot swappable add-in cards. The device operates from a wide supply range and generates the signals necessary to drive an isolated output DC/DC converter. As a typical add-in board is inserted into the powered backplane, physical connections must first be made with the chassis to discharge any electrostatic voltage potentials. The board then contacts the long pins on the backplane that provide power and ground. As soon as power is applied, the device starts up, but does not immediately apply power to the output load. Under-voltage and over-voltage circuits inside the controller verify the input voltage is within the user-specified range. Once these requirements are met, the hot-swap controller enables VGATE to turn on the external power MOSFET. The VGATE output is current limited to IVGATE, allowing the slew rate to be easily modified using external passive GENERAL DESCRIPTION components. During the controlled turn-on period the VDS of the MOSFET is monitored by the DRAIN SENSE input. When DRAIN SENSE drops below 2.5V, and VGATE is greater than VDD – VGT, the PG# output can begin turning on the DC/DC converter. Steady state operation is maintained as long as all conditions are normal. Any of the following events may cause the device to disable the DC/DC controller by shutting down the power MOSFET: an under-voltage or over-voltage condition on the host power supply; an over- current event detected on the CBSENSE input; a failure of the power MOSFET sensed via the DRAIN SENSE pin; the master enable (EN/TS) falling below 2.5V; or the FS# input being driven low by events on the secondary side of the DC/DC controller. If one of these events occurs the SMH4802 can be configured so VGATE shuts off and either latches into an off state or recycles power after a cooling down period, tCYC. Figure 2. Functional Block diagram. Pin numbers reflect SOIC package. PROGRAMMED DELAY PROGRAMM- ABLE DELAY + – + – + – PROGRAMMED Quick-Trip 50mV DUTY CYCLE TIMER + – 5V 2.5V 12V VGATE SENSE + – VDD VSS CBSENSE EN/TS SCL SDA UV OV PG# DRAIN SENSE VGATE 5.0VREF 12VREF 2062 BD PROGRAMMABLE SHUTDOWN TIMER FS# 14 3 1 5 9 7 4 8 6 2 11 12 10 200k Ω I2C INTERFACE LOGIC 50k Ω 50k Ω PROGRAMM- ABLE DELAY OV/UV FILTER Prog. Ref. |
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