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HT48R10A-1 Datasheet(PDF) 9 Page - Holtek Semiconductor Inc |
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HT48R10A-1 Datasheet(HTML) 9 Page - Holtek Semiconductor Inc |
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9 / 37 page  HT48R10A-1/HT48C10-1 Rev. 2.01 9 January 9, 2009 cuting the ²HALT² or ²CLR WDT² instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or exe- cuting the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can cor- rupt the status register, precautions must be taken to save it properly. Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable or disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain in- terrupt requires servicing within the service routine, the EMI bit and the corresponding bit of INTC may be set to allow interrupt nesting. If the stack is full, the interrupt re- quest will not be acknowledged, even if the related inter- rupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from be- coming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro- gram memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. External interrupts are triggered by a high to low transi- tion of INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a sub- routine call to location 04H will occur. The interrupt re- quest flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 5 of INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other in- terrupt acknowledgments are held until the ²RETI² in- struction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to en- able an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter- rupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. No. Interrupt Source Priority Vector a External Interrupt 1 04H b Timer/Event Counter Overflow 2 08H Bit No. Label Function 0C C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. 1AC AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. 2 Z Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. 3OV OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. 4 PDF PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. 5TO TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. 6 ¾ Unused bit, read as ²0² 7 ¾ Unused bit, read as ²0² Status (0AH) Register |
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