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CXP858P56A Datasheet(PDF) 11 Page - Sony Corporation |
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CXP858P56A Datasheet(HTML) 11 Page - Sony Corporation |
11 / 22 page – 11 – CXP858P56A ∗1 V IN and VOUT should not exceed VDD + 0.3V. ∗2 The large current output port is Port D (PD) and Port F (PF). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Supply voltage Input voltage Output voltage Medium drive output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD Vpp VIN VOUT VOUTP IOH ΣIOH IOL IOLC ΣIOL Topr Tstg PD –0.3 to +7.0 –0.3 to +13.0 –0.3 to +7.0∗1 –0.3 to +7.0∗1 –0.3 to +15.0 –5 –50 15 20 100 –10 to +75 –55 to +150 1000 600 V V V V V mA mA mA mA mA °C °C mW mW Incorporated PROM PF0 to PF3 pins Total of all output pins Ports excluding large current outputs (value per pin) Large current output port (value per pin)∗2 Total of all output pins SDIP-64P-01 QFP-64P-L01 Item Symbol Ratings Unit Remarks Absolute Maximum Ratings (Vss = 0V reference) 5.5 5.5 5.5 5.5 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 V V V V V V V V V V V °C Item Symbol Min. Max. Unit Remarks 4.5 3.5 2.5 4.5 0.7VDD 0.8VDD VDD – 0.4 0 0 –0.3 –10 VDD ∗1 This device does not enter the stop mode. ∗2 PA, PB, PC, PE0 to PE1, SCL0 to SCL1, SDA0 to SDA1 pins. ∗3 INT2, SCK, SO, SI, HS0, HS1, RMC, EC, INT1, HSYNC, VSYNC, RST pins. ∗4 Specifies only during external clock input. ∗5 CV DD and VDD should be set to the same voltage. ∗6 Vpp and V DD should be set to the same voltage. Recommended Operating Conditions (Vss = 0V reference) Supply voltage Data slicer supply voltage High level input voltage Low level input voltage Operating temperature CVDD VIH VIHS VIHEX VIL VILS VILEX Topr Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks Guaranteed operation range for 1/16 frequency dividing clock or sleep mode Guaranteed data hold range for stop mode∗1 ∗6 ∗5 ∗2 ∗3 EXTAL pin∗4 ∗2 ∗3 EXTAL pin∗4 Vpp Vpp = VDD |
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