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ISL70227SEH Datasheet(PDF) 2 Page - Intersil Corporation |
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ISL70227SEH Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 18 page ISL70227SEH 2 FN7958.1 August 24, 2012 Pin Configuration Ordering Information ORDERING NUMBER (Notes 1, 2) PART MARKING TEMP RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # 5962R1222301VXA ISL70227SEHVF -55 to +125 10 Ld Flatpack K10.A ISL70227SEHF/PROTO ISL70227 SEHF/PROTO -55 to +125 10 Ld Flatpack K10.A 5962R1222301V9A ISL70227SEHVX -55 to +125 Die ISL70227SEHX/SAMPLE ISL70227SEHVX/SAMPLE -55 to +125 Die ISL70227MHEVAL1Z Evaluation Board NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70227SEH. For more information on MSL please see techbrief TB363. ISL70227SEH (10 LD FLATPACK) TOP VIEW Pin Descriptions PIN NUMBER PIN NAME EQUIVALENT CIRCUIT DESCRIPTION 3 +IN A Circuit 1 Amplifier A non-inverting input 5 V- Circuit 3 Negative power supply 7 +IN B Circuit 1 Amplifier B non-inverting input 8 -IN B Circuit 1 Amplifier B inverting input 9 OUT B Circuit 2 Amplifier B output 10 V+ Circuit 3 Positive power supply 1 OUT A Circuit 2 Amplifier A output 2 -IN A Circuit 1 Amplifier A inverting input 4, 6 NC - Not Connected – This pin is not electrically connected internally. 10 9 8 7 6 2 3 4 5 1 OUTA -IN A +IN A NC V- V+ OUT B -IN B +IN B NC + - + - V+ V- OUT CIRCUIT 2 CIRCUIT 1 V+ V- CIRCUIT 3 IN- V+ V- IN+ CAPACITIVELY TRIGGERED ESD CLAMP |
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