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CXP84548 Datasheet(PDF) 11 Page - Sony Corporation |
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CXP84548 Datasheet(HTML) 11 Page - Sony Corporation |
11 / 27 page – 11 – CXP84540/84548 28 pins PD0 to PD7 PF0 to PF7 PG0 to PG7 PI4 to PI7 IP Ports D, F, G, I data "0" when reset Ports D, F, G, I direction Pull-up resistor "0" when reset RD Data bus ∗ Pull-up transistor approx. 100k Ω (VDD = 4.5 to 5.5V) approx. 300k Ω (VDD = 3.0 to 3.6V) ∗ Port I 8 pins Hi-Z PH0 to PH7 Data bus RD (Port H) Port H direction IP Port H data Pull-up resistor "0" when reset "0" when reset Standby release Edge detection ∗ Pull-up transistor approx. 100k Ω (VDD = 4.5 to 5.5V) approx. 300k Ω (VDD = 3.0 to 3.6V) ∗ Port H 4 pins Hi-Z PI0/INT0 to PI3/INT3 Port D Port F Port G Port I Hi-Z Data bus IP Port I data "0" when reset ∗ Pull-up transistor approx. 100k Ω (VDD = 4.5 to 5.5V) approx. 300k Ω (VDD = 3.0 to 3.6V) ∗ Port I direction Pull-up resistor "0" when reset INT0 INT1 INT2 INT3 RD Schmitt input When reset Pin Circuit format |
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Similar Description - CXP84548 |
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