CY7C2262XV18, CY7C2264XV18

Document Number : 001-70330 Rev. *B

Page 6 of 29

Functional Overview

The CY7C2262XV18, and CY7C2264XV18 are synchronous

pipelined Burst SRAMs equipped with a read port and a write

port. The read port is dedicated to read operations and the write

port is dedicated to write operations. Data flows into the SRAM

through the write port and flows out through the read port. These

devices multiplex the address inputs to minimize the number of

address pins required. By having separate read and write ports,

the QDR II+ Xtreme completely eliminates the need to “turn

around” the data bus and avoids any possible data contention,

thereby simplifying system design. Each access consists of two

18-bit data transfers in the case of CY7C2262XV18, and two

36-bit data transfers in the case of CY7C2264XV18 in one clock

cycle.

These devices operate with a read latency of two and half cycles

when DOFF pin is tied HIGH. When DOFF pin is set LOW or

a read latency of one clock cycle.

Accesses for both ports are initiated on the rising edge of the

positive input clock (K). All synchronous input and output timing

are referenced from the rising edge of the input clocks (K and K).

controlled by the input clocks (K and K). All synchronous data

rising edge of the input clocks (K and K) as well.

through input registers controlled by the rising edge of the input

clocks (K and K).

CY7C2262XV18 is described in the following sections. The

same basic descriptions apply to CY7C2264XV18.

Read Operations

The CY7C2262XV18 is organized internally as two arrays of

1 M × 18. Accesses are completed in a burst of two sequential

18-bit data words. Read operations are initiated by asserting

RPS active at the rising edge of the positive input clock (K). The

address is latched on the rising edge of the K clock. The address

presented to the address inputs is stored in the read address

register. Following the next two K clock rise, the corresponding

K as the output timing reference. On the subsequent rising edge

requested data is valid 0.45 ns from the rising edge of the input

clock (K and K).

When the read port is deselected, the CY7C2262XV18 first

completes the pending read transactions. Synchronous internal

circuitry automatically tristates the outputs following the next

rising edge of the negative input clock (K). This enables for a

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF

Input

PLL Turn Off

 Active LOW. Connecting this pin to ground turns off the PLL inside the device. The

timing in the operation with the PLL turned off differs from those listed in this data sheet. For normal

operation, connect this pin to a pull up through a 10 k

 or less pull up resistor. The device behaves in

QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up

to 167 MHz with QDR I timing.

TDO

Output

TDO Pin for JTAG.

TCK

Input

TCK Pin for JTAG.

TDI

Input

TDI Pin for JTAG.

TMS

Input

TMS Pin for JTAG.

NC

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/72M

Input

Not Connected to the Die. Can be tied to any voltage level.

NC/144M

Input

Not Connected to the Die. Can be tied to any voltage level.

NC/288M

Input

Not Connected to the Die. Can be tied to any voltage level.

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC

measurement points.

Power Supply Power Supply Inputs to the Core of the Device.

Ground

Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

Pin Name

I/O

Pin Description