CY7C1460BV25 datasheet(1/30 Pages) CYPRESS

Part #	CY7C1460BV25

Description	36-Mbit (1 M 횞 36/2 M 횞 18) Pipelined SRAM with NoBL??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C1460BV25

CY7C1462BV25

36-Mbit (1 M × 36/2 M × 18)

Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

, CA 95134-1709

•

408-943-2600

Document Number: 001-74446 Rev. *C

Revised October 25, 2012

36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture

Features

■ Pin-compatible and functionally equivalent to ZBT™

■ Supports 250-MHz bus operations with zero wait states

❐ Available speed grades is 250 MHz

■ Internally self-timed output buffer control to eliminate the need

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte Write capability

■ 2.5 V core power supply

■ 2.5 V/1.8 V I/O power supply

■ Fast clock-to-output times

❐ 2.6 ns (for 250-MHz device)

■ Clock enable (CEN) pin to suspend operation

■ Synchronous self-timed writes

■ CY7C1460BV25,

CY7C1462BV25 available in Pb-free

165-ball FBGA package and CY7C1462BV25 available in

JEDEC-standard Pb-free 100-pin TQFP package

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ Burst capability – linear or interleaved burst order

■ “ZZ” sleep mode option and stop clock option

Functional Description

The

CY7C1460BV25/CY7C1462BV25

are

2.5 V,

1 M × 36/2 M × 18 synchronous pipelined burst SRAMs with No

Bus Latency™ (NoBL

 logic, respectively. They are designed

to support unlimited true back-to-back read/write operations with

no wait states. The CY7C1460BV25/CY7C1462BV25 are

equipped with the advanced NoBL logic required to enable

consecutive read/write operations with data being transferred on

every clock cycle. This feature dramatically improves the

throughput of data in systems that require frequent write/read

transitions.

The

CY7C1460BV25/CY7C1462BV25

are

pin-compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the clock enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle. Write operations are controlled by the byte write selects

(BWa–BWd

for

CY7C1460BV25

and

BWa–BWb

for

CY7C1462BV25) and a write enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous chip enables (CE1, CE2, CE3) and an

asynchronous output enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram – CY7C1460BV25

A0, A1, A

C

MODE

BWa

BWb

WE

CE1

CE2

CE3

OE

READ LOGIC

DQs

DQPa

DQPb

DQPc

DQPd

D

A

T

A

S

T

E

R

I

N

G

O

U

T

P

U

T

B

U

F

E

R

S

MEMORY

ARRAY

E

INPUT

REGISTER 0

ADDRESS

REGISTER 0

WRITE ADDRESS

REGISTER 1

WRITE ADDRESS

REGISTER 2

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

D1

D0

Q1

Q0

A0

A1

C

ADV/LD

E

INPUT

REGISTER 1

S

E

N

S

E

A

M

P

S

E

CLK

CEN

WRITE

DRIVERS

BWc

BWd

ZZ

SLEEP

CONTROL

O

U

T

P

U

T

R

E

G

I

S

T

E

R

S

Similar Part No. - CY7C1460BV25

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CY7C1460BV25 Datasheet(PDF) 1 Page - Cypress Semiconductor

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