Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

U74AC74 Datasheet(PDF) 4 Page - Unisonic Technologies

Part # U74AC74
Description  POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
Download  6 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  UTC [Unisonic Technologies]
Direct Link  http://www.utc-ic.com
Logo UTC - Unisonic Technologies

U74AC74 Datasheet(HTML) 4 Page - Unisonic Technologies

  U74AC74 Datasheet HTML 1Page - Unisonic Technologies U74AC74 Datasheet HTML 2Page - Unisonic Technologies U74AC74 Datasheet HTML 3Page - Unisonic Technologies U74AC74 Datasheet HTML 4Page - Unisonic Technologies U74AC74 Datasheet HTML 5Page - Unisonic Technologies U74AC74 Datasheet HTML 6Page - Unisonic Technologies  
Zoom Inzoom in Zoom Outzoom out
 4 / 6 page
background image
U74AC74
CMOS IC
UNISONICTECHNOLOGIESCO.,LTD
4 of 6
www.unisonic.com.tw
QW-R502-800.A
DYNAMIC CHARACTERISTICS
TA=25°C, unless otherwise specified, Input: tR, tF≤2.5ns; PRR≤1MHz
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNIT
Clock frequency
FCLOCK VCC=3V±0.3V
100
MHZ
Pulse duration
tw
VCC=3V±0.3V, PRE or CLR in Low
5.5
ns
VCC=3V±0.3V, CLK
5.5
Setup time before CLK↑
tsu
VCC=3V±0.3V, PRE or CLR inactive
0
ns
Data
4
Hold time ,data after CLK↑
th
VCC=3V±0.3V
0.5
ns
Clock frequency
FCLOCK VCC=5V±0.5V
140
MHz
Pulse duration
tw
VCC=5V±0.5V, PRE or CLR in Low
4.5
ns
VCC=3V±0.3V, CLK
4.5
Setup time before CLK↑
tsu
VCC=5V±0.5V, PRE or CLR inactive
0
ns
Data
3
Hold time ,data after CLK↑
th
VCC=5V±0.5V
0.5
ns
DYNAMIC CHARACTERISTICS (See Fig. 1 and Fig. 2 for test circuit and waveforms.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNIT
Maximum clock
FMAX
VCC=3V±0.3V, CL=50pF, RL=500Ω
100
125
MHz
Propagation delay from input
( PRE or CLR ) to output(Q or Q)
tPLH
VCC=3V±0.3V, CL=50pF, RL=500Ω
3.5
8
12
ns
tPHL
4
10.5
12
Propagation delay from input
(CLK) to output(Q or Q)
tPLH
VCC=3V±0.3V, CL=50pF, RL=500Ω
4.5
8
13.5
ns
tPHL
3.5
8
14
Maximum clock
FMAX
VCC=5V±0.5V
140
160
MHz
Propagation delay from input
( PRE or CLR ) to output(Q or Q)
tPLH
VCC=5V±0.5V, CL=50pF, RL=500Ω
2.5
6
9
ns
tPHL
3
8
9.5
Propagation delay from input
(CLK) to output(Q or Q)
tPLH
VCC=5V±0.5V, CL=50pF, RL=500Ω
3.5
6
10
ns
tPHL
2.5
6
10
OPERATING CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNIT
Power Dissipation Capacitance
Cpd
CL=50p, f=1MHz, VCC=3.3V
45
pF


Similar Part No. - U74AC74

ManufacturerPart #DatasheetDescription
logo
Unisonic Technologies
U74AC74G-S14-R UTC-U74AC74G-S14-R Datasheet
170Kb / 6P
   DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
U74AC74L-S14-R UTC-U74AC74L-S14-R Datasheet
170Kb / 6P
   DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
U74AC74 UTC-U74AC74_15 Datasheet
170Kb / 6P
   DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
More results

Similar Description - U74AC74

ManufacturerPart #DatasheetDescription
logo
Texas Instruments
SN74HC74-Q1 TI1-SN74HC74-Q1_15 Datasheet
828Kb / 14P
[Old version datasheet]   DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC2G74 TI1-SN74LVC2G74_18 Datasheet
1Mb / 25P
[Old version datasheet]   Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset
SN74LVC2G74 TI-SN74LVC2G74 Datasheet
355Kb / 15P
[Old version datasheet]   SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
74ACT11074 TI-74ACT11074 Datasheet
81Kb / 5P
[Old version datasheet]   DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74AUC1G74 TI-SN74AUC1G74 Datasheet
266Kb / 12P
[Old version datasheet]   SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC2G74-EP TI1-SN74LVC2G74-EP Datasheet
451Kb / 12P
[Old version datasheet]   SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC2G74 TI-SN74LVC2G74_08 Datasheet
440Kb / 14P
[Old version datasheet]   SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
SN74HC74-EP TI1-SN74HC74-EP Datasheet
600Kb / 12P
[Old version datasheet]   DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET
SN74AHCT74-EP TI1-SN74AHCT74-EP Datasheet
434Kb / 9P
[Old version datasheet]   DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
74AC11074 TI-74AC11074 Datasheet
92Kb / 6P
[Old version datasheet]   DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
REVISED APRIL 1996
More results


Html Pages

1 2 3 4 5 6


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com