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CXK5T81000ATN Datasheet(PDF) 5 Page - Sony Corporation

Part No. CXK5T81000ATN
Description  131072-word X 8-bit High Speed CMOS Static RAM
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Maker  SONY [Sony Corporation]
Homepage  http://www.sony.co.jp
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CXK5T81000ATN/AYN
• Read cycle (WE = “H”)
1 t
HZ1
, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
2 t
WHZ
is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
• Write cycle
Item
Symbol
Min.
Max.
Min.
Max.
-10LLX
VCC = 2.7 to 3.6V
VCC = 3.3V ± 0.3V
-12LLX
Unit
tRC
tAA
tCO1
tCO2
tOE
tOH
tLZ1
tLZ2
tOLZ
tHZ11
tHZ21
tOHZ1
100
10
10
5
100
100
100
50
40
35
120
10
10
5
120
120
120
60
40
35
Min.
Max.
Min.
Max.
-10LLX
-12LLX
85
10
10
5
85
85
85
40
35
30
100
10
10
5
100
100
100
50
40
35
Read cycle time
Address access time
Chip enable access time (CE1)
Chip enable access time (CE2)
Output enable to output valid
Output hold from address change
Chip enable to output in low Z
(CE1, CE2)
Output enable to output in low Z (OE)
Chip disable to output in high Z
(CE1, CE2)
Output disable to output in high Z (OE)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Item
Symbol
Min.
Max.
Min.
Max.
-10LLX
VCC = 2.7 to 3.6V
VCC = 3.3V ± 0.3V
-12LLX
Unit
tWC
tAW
tCW
tDW
tDH
tWP
tAS
tWR
tWR1
tOW
tWHZ2
100
80
80
40
0
70
0
0
0
5
40
120
100
100
50
0
70
0
0
0
5
40
Min.
Max.
Min.
Max.
-10LLX
-12LLX
85
70
70
35
0
60
0
0
0
5
35
100
80
80
40
0
70
0
0
0
5
40
Write cycle time
Address valid to end of write
Chip enable to end of write
Data to write time overlap
Data hold from write time
Write pulse width
Address setup time
Write recovery time (WE)
Write recovery time (CE1, CE2)
Output active from end of write
Write to output in high Z
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns




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