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M2S080T-FGG144Y Datasheet(PDF) 11 Page - Microsemi Corporation |
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M2S080T-FGG144Y Datasheet(HTML) 11 Page - Microsemi Corporation |
11 / 156 page SmartFusion2 System-on-Chip FPGAs R e visio n 0 1 -3 Data Security Data security is protecting the information the FPGA is storing, processing, or communicating in its role in the end application. If, for example, the configured design is implementing the key management and encryption portion of a secure military radio, data security could entail encrypting and authenticating the radio traffic, and protecting the associated application-level cryptographic keys. Data security is closely related to the terms information assurance (IA) and information security. All SmartFusion2 devices incorporate enhanced design security, making them the most secure programmable logic devices ever made. Select SmartFusion2 models also include an advanced set of on-chip data security features that make designing secure information assurance applications easier and better than ever before. The following are the main data security features supported: • Non-deterministic random bit generator (NRBG) service • User Cryptographic services (e.g., AES-128/-256, SHA-256, and HMAC) • Hardware firewalls protecting MSS memories • Cryptography Research Inc. (CRI) pass-through Differential Power Analysis (DPA) Patent Portfolio license • The M2S080 and M2S120 also have the following features: – Elliptic Curve Cryptography (ECC) cryptographic computation services – User PUF key enrollment and regeneration for advanced design and data security applications Low Power Microsemi’s flash-based FPGA fabric results in extremely low power design implementation with static power on the M2S050 device as low as 10 mW. Flash*Freeze (F*F) technology provides an ultra-low power static mode (Flash*Freeze mode) for SmartFusion2 devices, with power less than 1 mW. F*F mode entry retains all the SRAM and register information and the exit from F*F mode achieves rapid recovery to active mode. High Performance FPGA Fabric Built on 65 nm process technology, the SmartFusion2 FPGA fabric is composed of 4 building blocks: the logic module, the large SRAM, the micro SRAM and the Math block. The logic module is the basic logic element and has advanced features: • A fully permutable 4-input LUT (look-up table) optimized for lowest power • A dedicated carry chain based on carry look-ahead technique • A separate flip-flop which can be used independently from the LUT The 4-input look-up table can be configured either to implement any 4-input combinatorial function or to implement an arithmetic function where the LUT output is XORed with carry input to generate the sum output. Dual-Port Large SRAM (LSRAM) Large SRAM (RAM1Kx18) is targeted for storing large memory for use with various operations. Each LSRAM block can store up to 18,432 bits. Each RAM1Kx18 block contains two independent data ports: Port A and Port B. The LSRAM is synchronous for both Read and Write operations. Operations are triggered on the rising edge of the clock. The data output ports of the LSRAM have pipeline registers which have control signals that are independent of the SRAM’s control signals. Three-Port Micro SRAM (uSRAM) Micro SRAM (RAM64x18) is the second type of SRAM which is embedded in the fabric of SmartFusion2 devices. RAM64x18 uSRAM is a 3-port SRAM; it has two read ports (Port A and Port B) and one write |
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