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STA382BW Datasheet(PDF) 6 Page - STMicroelectronics |
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STA382BW Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 172 page Contents STA382BW 6/172 Doc ID 022783 Rev 1 6.26.3 Extended biquad selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.27 PLL configuration registers (address 0x52; 0x53; 0x54; 0x55; 0x56; 0x57) . . . . . . . . . . . . . . . . . . . . 88 6.28 Short-circuit protection mode registers SHOK (address 0x58) . . . . . . . . 90 6.29 Extended coefficient range up to -4...4 (address 0x5A) . . . . . . . . . . . . . . 91 6.30 Miscellaneous registers (address 0x5C, 0x5D) . . . . . . . . . . . . . . . . . . . . 92 6.30.1 Rate power-down enable (RPDNEN) bit . . . . . . . . . . . . . . . . . . . . . . . . 92 6.30.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . . 92 6.30.3 Channel PWM enable (CPWMEN) bit . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.30.4 External amplifier hardware pin enabler (LPDP, LPD LPDE) bits . . . . . 93 6.30.5 Power-down delay selector (PNDLSL[2:0]) bits . . . . . . . . . . . . . . . . . . . 93 6.30.6 Short-circuit check enable bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.31 Bad PWM detection registers (address 0x5E, 0x5F, 0x60) . . . . . . . . . . . 94 6.32 Enhanced zero-detect mute and input level measurement (address 0x61-0x65, 0x3F, 0x40, 0x6F) . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.33 Headphone/Line out configuration register (address 0x66) . . . . . . . . . . . 97 6.34 F3XCFG (address 0x69; 0x6A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.35 STCompressorTM configuration register (address 0x6B; 0x6C) . . . . . . . . 99 6.36 Charge pump synchronization (address 0x70) . . . . . . . . . . . . . . . . . . . . . 99 6.37 Coefficient RAM CRC protection (address 0x71-0x7D) . . . . . . . . . . . . . 100 6.38 MISC4 (address 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7 Register description: Sound Terminal compatibility . . . . . . . . . . . . . 104 7.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.1.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.1.2 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.1.3 Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.2.1 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.2.2 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.2.3 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.2.4 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.2.5 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.3.1 FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 |
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