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PE42551 Datasheet(PDF) 4 Page - Peregrine Semiconductor Corp. |
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PE42551 Datasheet(HTML) 4 Page - Peregrine Semiconductor Corp. |
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4 / 9 page  Product Specification PE42551 Page 4 of 9 Document No. 70-0350-02 │ www.psemi.com ©2010-2012 Peregrine Semiconductor Corp. All rights reserved. 50 OHM T-Line 50 OHM T-Line 50 OHM T-Line 50 OHM T-Line J2 SMASM J2 SMASM 1 J5 SMASM J5 SMASM 1 R1 1M R1 1M J6 HEADER 7X2 J6 HEADER 7X2 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 12 12 14 14 13 13 9 9 11 11 R2 1M R2 1M J3 SMASM J3 SMASM 1 J4 SMASM J4 SMASM 1 U1 PE42551 GND 2 RF1 3 GND 4 GND 5 GND 1 GND 12 GND 11 RF2 13 GND 14 GND 15 J1 SMASM J1 SMASM 1 C3 DNI C3 DNI C2 DNI C2 DNI C1 DNI C1 DNI Evaluation Kit The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE42551 SPDT switch. The RF common port is connected through a 50 Ω transmission line to J2. Port 1 and Port 2 are connected through 50 Ω transmission lines to J1 and J3. A through transmission line connects SMA connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a two metal layer FR4 material with a total thickness of 0.032”. The transmission lines were designed using a coplanar waveguide with ground plane (28 mil core, 47.6 mil width, 30 mil gap). Good RF layout and prudent use of vias is critical for obtaining the specified isolation performance for the device shown in this datasheet. J6 provides a means for controlling DC and digital inputs to the device. The provided jumpers short the package pin to ground for logic low. When the jumper is removed, the pin is pulled up to VDD for logic high. When the jumper is in place, 3 µA of current will flow through the 1MΩ pull up resistor. This extra current should not be attributed to the requirements of the device. Figure 5. Evaluation Board Layouts Figure 6. Evaluation Board Schematic Peregrine Specification 102-0198 Peregrine Specification 101-0151 |
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