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STULPI01A Datasheet(PDF) 8 Page - STMicroelectronics |
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STULPI01A Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 44 page Bump configuration STULPI01A, STULPI01B 8/44 Doc ID 14817 Rev 4 Bump Symbol Type Description F1 NC Not connected F2 NC Not connected. E2 VB_REF_FAULT I Voltage reference for internal OC detector input or digital input from external OC detector (V3V3V referred). 5 V tolerant. D4 PSWn O External charge pump control, active low. 5 V tolerant, open drain. F5 XI I External clock input (VDVIO referred). F6 XO O XO pin must be left floating or grounded (crystal is not supported). F3 VBAT PWR Battery power input for the LDO (3 V – 4.5 V). Bypass VBAT to GND with a 1 µF capacitor. E3 3V3V PWR 3.3 V LDO output. Bypass 3V3V to GND with a 1.5 µF capacitor. E6 1V2V PWR 1.2 V LDO output. Bypass 1V2V to GND with a 1.5 µF capacitor. C2 RREF I/O Reference resistor (12 k Ω ±1%) B2/B3/B5 VDVIO PWR Digital I/O supply voltage. Bypass each VDVIO to GND with a 100 nF-1 μF capacitor. Balls B2-B5 can share common capacitor. C5/D2 GND PWR Ground B4/E4/E1 GND PWR Ground Table 2. Pinout and bump description (continued) |
Similar Part No. - STULPI01A_12 |
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Similar Description - STULPI01A_12 |
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