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CXD2470R

Serial interface clock output variation characteristics

Normally, the serial interface data is loaded to the CXD2470R at the timing shown in "Serial interface clock

internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is

loaded to the CXD2470R and controlled at the rising edge of SEN. See "Description of Operation".

SEN

Output signal

tpdPULSE

Symbol

tpdPULSE

Definition

Output signal delay, activated by the rising edge of SEN

Min.

Typ.

Max.

100

5

Unit

ns

(Within the recommended operating conditions)

Serial interface clock internal loading characteristics (2)

th1

Enlarged view

ts1

VDI

HDI

VDI

HDI

SEN

Example: During frame mode

Symbol

Definition

SEN setup time, activated by the falling edge of VDI

SEN hold time, activated by the falling edge of VDI

Min.

Typ.

Max.

0

200

Unit

ns

ns

∗ Be sure to maintain a constantly high SEN logic level near the falling edge of VDI.

(Within the recommended operating conditions)