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IS49NLS18320 Datasheet(PDF) 2 Page - Integrated Silicon Solution, Inc |
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IS49NLS18320 Datasheet(HTML) 2 Page - Integrated Silicon Solution, Inc |
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2 / 34 page  IS49NLS96400,IS49NLS18320 Integrated Silicon Solution, Inc. – www.issi.com – Rev. 00E, 06/20/2012 2 1 Package Ballout and Description 1.1 576Mb (64Mx9) Separate I/O BGA Ball‐out (Top View) 1 2 3 4 5678 9 10 11 12 A VREF VSS VEXT VSS VSS VEXT TMS TCK B VDD DNU 3 DNU 3 VSSQ VSSQ Q0 D0 VDD C VTT DNU 3 DNU 3 VDDQ VDDQ Q1 D1 VTT D A22 1 DNU 3 DNU 3 VSSQ VSSQ QK0# QK0 VSS E A21 DNU 3 DNU 3 VDDQ VDDQ Q2 D2 A20 F A5 DNU 3 DNU 3 VSSQ VSSQ Q3 D3 QVLD G A8 A6 A7 VDD VDD A2 A1 A0 H BA2 A9 VSS VSS VSS VSS A4 A3 J NF 2 NF 2 VDDVDD VDDVDD BA0 CK K DK DK# VDD VDD VDD VDD BA1 CK# L REF# CS# VSS VSS VSS VSS A14 A13 M WE# A16 A17 VDD VDD A12 A11 A10 N A18 DNU 3 DNU 3 VSSQ VSSQ Q4 D4 A19 P A15 DNU 3 DNU 3 VDDQ VDDQ Q5 D5 DM R VSS DNU 3 DNU 3 VSSQ VSSQ Q6 D6 VSS T VTT DNU 3 DNU 3 VDDQ VDDQ Q7 D7 VTT U VDD DNU 3 DNU 3 VSSQ VSSQ Q8 D8 VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI Symbol Description Ball count VDD Supply voltage 16 VSS Ground 16 VDDQ DQ power supply 8 VSSQ DQ Ground 12 VEXT Supply voltage 4 VREF Reference voltage 2 VTT Termination voltage 4 A* Address ‐ A0‐22 23 BA* Banks ‐ BA0‐23 D* Input data 9 Q* Output data 9 DK* Input data clock(Differential inputs) 2 QK* Output data clocks(outputs) 2 CK* Input clocks (CK, CK#) 2 DM Input data mask 1 CS#,WE#,REF# Command control pins 3 ZQ External impedance (25–60Ω)1 QVLD Data valid 1 DNU,NF Do not use, No function 22 T* JTAG ‐ TCK,TMS,TDO,TDI 4 Total 144 NOTES: 1) Reserved for future use. This may optionally be connected to GND. 2) Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to GND. 3) No function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to GND. 4) Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins will be connected to VTT. NOTES: 1) Reserved for future use. This may optionally be connected to GND. 2) Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to GND. Notes: 1. Reserved for future use. This may optionally be connected to GND. 2. No function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to GND. 3. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins are High‐Z. |
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