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TC62D748CFG Datasheet(PDF) 9 Page - Toshiba Semiconductor |
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TC62D748CFG Datasheet(HTML) 9 Page - Toshiba Semiconductor |
9 / 23 page TC62D748CFG 2011-12-14 9 Switching Characteristics (Unless otherwise specified, VDD = 3.3V, Ta = 25°C) Characteristics Symbol Test Circuits Test Conditions Min Typ. Max Unit SCK- OUT0 tpLH1 6 SLAT = “H”, OE = “L” ⎯ 50 65 ns SLAT - OUT0 tpLH2 6 OE = “L” ⎯ 50 65 ns OE - OUT0 tpLH3 6 SLAT = “H” ⎯ 50 65 ns SCK-SOUT tpLH 6 CL=10.5 pF 10 20 35 ns SCK- OUT0 tpHL1 6 SLAT = “H”, OE = “L” ⎯ 30 40 ns SLAT - OUT0 tpHL2 6 OE = “L” ⎯ 30 40 ns OE - OUT0 tpHL3 6 SLAT = “H” ⎯ 30 40 ns Propagation delay time SCK-SOUT tpHL 6 CL=10.5 pF 10 20 35 ns Output rise t i me tor 6 10 to 90% of voltage waveform ⎯ 30 45 ns Output fall t i m e tof 6 90 to 10% of voltage waveform ⎯ 10 20 ns twOE(L) 6 OE = “L” 25 ⎯ ⎯ Enabl e pulse w i d th twOE(H) 6 OE = “H” 50 ⎯ ⎯ ns Cl ock p u l s e wi d t h twSCK 6 SCK = “H” or “L” 20 ⎯ ⎯ ns Latch pulse w i d th twSLAT 6 SLAT = “H” 20 ⎯ ⎯ ns Switching Characteristics (Unless otherwise specified, VDD = 5.0V, Ta = 25°C) Characteristics Symbol Test Circuits Test Conditions Min Typ. Max Unit SCK- OUT0 tpLH1 6 SLAT = “H”, OE = “L” ⎯ 50 65 ns SLAT - OUT0 tpLH2 6 OE = “L” ⎯ 50 65 ns OE - OUT0 tpLH3 6 SLAT = “H” ⎯ 50 65 ns SCK-SOUT tpLH 6 CL=10.5 pF 10 20 35 ns SCK- OUT0 tpHL1 6 SLAT = “H”, OE = “L” ⎯ 30 40 ns SLAT - OUT0 tpHL2 6 OE = “L” ⎯ 30 40 ns OE - OUT0 tpHL3 6 SLAT = “H” ⎯ 30 40 ns Propagation delay time SCK-SOUT tpHL 6 CL=10.5 pF 10 20 35 ns Output rise t i me tor 6 10 to 90% of voltage waveform ⎯ 30 45 ns Output fall t i m e tof 6 90 to 10% of voltage waveform ⎯ 10 20 ns twOE(L) 6 OE = “L” 25 ⎯ ⎯ Enabl e pulse w i d th twOE(H) 6 OE = “H” 50 ⎯ ⎯ ns Cl ock p u l s e wi d t h twSCK 6 SCK = “H” or “L” 20 ⎯ ⎯ ns Latch pulse w i d th twSLAT 6 SLAT = “H” 20 ⎯ ⎯ ns |
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